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Recent content by mark_yeh

  1. M

    How to deal with the practical dsp in ASIC design?

    i think you should obtain more experient of ASIC design before you read the book <VLSI Digital Signal Processing Systems, Design and Implementation>. so you can make a bridge between the algorithms the book mentioned and the implemention in your mind.
  2. M

    Timing and logic stage for FPGA

    what dose "logic levels" mean? and how to decrease the logic levels in HDL code? thanks.
  3. M

    Timing Closure in front-end design

    Re: Timing Closure you use the wrong title "timing clusure". it is not about timing closure, it is about timing performance.
  4. M

    Fanout_Load value of an input in Synopsys DC

    you can calcute the fanout load by yourself based on the library information. you can specify a big fanout_load value to save area. but it must meet the timing constrain. if you wanna get high speed performance, the fannout_load value should be small.
  5. M

    Problem with timing closure in FPGA

    about timing closure hi all, i found the timing report from the synthesis tool is different very much from the timing report after place and route when i use xilinx devices. and the net delay is 70% and more after place and route. so i think that is timing closure problem. andbody here can...
  6. M

    Are the inserted samples in multirate sampling always zero?

    Re: Multirate you can read the elementary notes about multirate.
  7. M

    Writing MODEL for synthesis

    the model is not for verification, but for synthesesis instead? i don't understand. but if you write model by using verilog, you don't need much special skills. it's not difficult actually.
  8. M

    RTL Encounter VS Design Compiler

    the AE from Cadence told me that the design synthesized by their synthesis tool RTL Encounter(RC) is much smaller than by DC(2004.06), and saves much run time. but i am not sure. did anybody here compare the two tools with your own design ?
  9. M

    Are the inserted samples in multirate sampling always zero?

    Re: Multirate Generally. zeros are inserted between the original samples, but not always.
  10. M

    .13 vs .18 process - some ideas needed

    Re: .13 vs .18 i don't think the timing report is precision, espcially in .13 process. you should get the sdf file and back-annotate to the netlist. and then you can compare the tow timing reports, and get the result correctly.
  11. M

    Verilog question - do you use linting tools?

    nLint from Debussy is a good tool to do this.
  12. M

    How to find all combinatorial path from inputs to outputs ?

    Re: about synthesis If you are using DC, there are no commands to find the combinatorial paths. Just read the HDL code, or use HDL analyser such as Debussy.
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