mark_yeh
Newbie level 6
about timing closure
hi all,
i found the timing report from the synthesis tool is different very much from the timing report after place and route when i use xilinx devices. and the net delay is 70% and more after place and route. so i think that is timing closure problem. andbody here can share the experience about the timing closure in fpga with us?
thanks!
hi all,
i found the timing report from the synthesis tool is different very much from the timing report after place and route when i use xilinx devices. and the net delay is 70% and more after place and route. so i think that is timing closure problem. andbody here can share the experience about the timing closure in fpga with us?
thanks!