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Recent content by manju540

  1. M

    During Synthesi, if we won't provide a clock

    Hi, During Synthesis if we won't provide any clock source .... .how tool will react where we are using clock in RTL design & how it converts in to netlist.
  2. M

    Cannot write to a CFI FLASH through a state machine implemented in Verilog

    Re: Writing to CFI Flash HI akashiappa, I want to know how spansions cfi controller is going to work ... at least blocks and their functionality's in controller. Thanx in ADV manju540
  3. M

    Amba ahb htrans[1:0] states

    Hi, I have a doubt regarding HTRANS in AHB. In a HTRANS states are idle, busy, nonseq, seq. During transaction is BUSY state occur after IDLE state.can any one explain.
  4. M

    M-tech fresher seeking for VLSI jobs

    in sicontech hyd there is openings for who completed Physical Design Course .................
  5. M

    CMOS working principal ...... channel forming

    Hi I have a doubt that how Cmos is working ....A positive voltage applied to the gate, attracts electrons to the interface between the gate dielectric and the semiconductor . INVERTION layer is forming in mosfet ....for that where we can get electrons i mean that from substrate or source
  6. M

    Help to learn Physical Design concepts

    Than Q bird 123 .................for ur valuable suggestion
  7. M

    Help to learn Physical Design concepts

    Hi , Can any one explain the following .... 1. Manufacturing Grid 2.Routing Grid 3.Standard Cell Placement Info 4. Routing Layer Definition 5. Placement & Routing blockage layer Definition 6.Via definition 7. Conducting Layer Density Rule 8.Metal layer Slotting Rule 9.Routing Layer...
  8. M

    routing layers during pnr

    Hi, I am getting confusion about layers can any one explain about layers and how to avoid routing congestion by using layers Adv Thanx...
  9. M

    Help neded for to do Scan Stitching by using RTL Compiler

    tahnQ ranger01 ........................
  10. M

    DFT by using Cadence RTL COMPILER

    HI, Can any one help me how to define test_mode ,shift_enable,scan_chain in cadence rtl compiler ..................there are so may options are their for every command, which option i want to use i am not getting so plz can u help...
  11. M

    in RTL COMPILER i'm getting error at "define_dft shift_enable" command

    ThanQ for your advice im using version 10.1 only ,but hear so many options are their , so im getting confuse ... which one 2 apply
  12. M

    in RTL COMPILER i'm getting error at "define_dft shift_enable" command

    Hi I am using RTL Compiler im using muxed scan style ....but i dont know how to insert shift enable and test mode ,scan chain......to my DUT . can any budy explain with an example...
  13. M

    Help neded for to do Scan Stitching by using RTL Compiler

    hello i want to know about SCAN STITCHING can any one explain what is SCAN STITCHING and the command in RTL Compiler with adv thanx manju540
  14. M

    RTL Compiler: check_design command

    Hi kbulusu nice discussion can you help me how we can say that, which attribute is suitable for our design. because i saw that so many attributes but we use few of them
  15. M

    cmd & tcl for soc encounter

    hello arjun can i know how much extent to know Tcl scripts of foundation flow is needed.I mean to say yhat every thing in that script should learn before begging the tool. what is the useful of that tcl scripts
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