During Synthesi, if we won't provide a clock

[manju540]

Hi,
During Synthesis if we won't provide any clock source .... .how tool will react where we are using clock in RTL design & how it converts in to netlist.

 

[artmalik]

The design will still work , basically the tool will treat the block a synthesisable block and come up with gates. For example if you have 128 bit adder, the tool will come up with an adder with the smallest area. As you improve the constraints like speed and power the tool will optimize the speed of the design as it goes along. Nothing special about having a combination design in synthesis.

 

[jirika]

Synthesis tool knows DFFs and assume the wire connected to their CLK node is clock. So it won't create any buffers in this tree. But as was said it will work anyway.