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Recent content by love_analog

  1. L

    LVS issues of APR block

    I'm an analog guy trying to make sense of digital tools a) once you APR a block through ICC, do you do a LVS on APR output. If so, how? for synthesis I know you do conformal or some equivalence checking, what do you do after Layout. do you compare the CEL format with Gate level netlist or RTL...
  2. L

    Do people not use common centroid layout anymore?

    I believe at smaller process geometries 28nm etc. common-centroid is no longer that used. The layout complexity of having all these metals running around is too much. I have seen people use interdigitization and then put enough dummies to make sure influence distance is taken care of. I would...
  3. L

    How to decrease the variation of bandgap output voltage?

    Sorry erikl, I tend to disagree. The paper seems to talk about matching. The OP has done everything. The tempco is zero at ~center. I think the only thing he can do is curvature compensation. Extra trimming etc. won't make anything better.
  4. L

    Low Pass Sallen Key Filter design

    Agree with Milad-D. I implemeted 6th order filter this way in 1995. This was upto 4MHz. I don't know why FvM is saying use discrete components.
  5. L

    How to increase the resolution of comparator in SAR ADC?

    Gain might not help in offset (unless the succeeding stages are the ones causing the offset). One way would be to use techniques such as auto-zeroing, correlated double sampling etc.
  6. L

    switched cap circuit issue

    I haven't simulated Switch cap in a while but this basic question came up. The feedback in SC is caps (albeit with switches). So there is no real DC feedback. Then how can you actually simulated a switch cap amplifier for stability.
  7. L

    What is the major difference between CML and LVDS?

    People tend to equate LVDS with lower current than CML. Typically CML is used for highest freq ~10G or so.
  8. L

    transient simulation for feedback stability

    Say I have a feedback loop and I want to check stability of it through transients. How do I figure out what transient amplitude (ie step input amplitude) and rise time do I put as stimulus. do I put 5mV? 20mV ? 100mV Is the rise time 5ps? 20ps? 100ps?
  9. L

    What is the advantage and disadvantage of leging in layout

    Legging. Same as fingering. You break a large W/L into smaller ones. Helps in reducing gate resistance and the S/D - substrate cap
  10. L

    Concern of connecting thin-oxide device to ground/power

    I dug around somewhat. It seems that we use tie-low because you don't want to connect directly to Vcc. so you create a softvcc. However, we don't use a tie-high. Its okay to connect a gate directly to ground.
  11. L

    Question about timing engines in PnR tools

    PnR question You can put many constraints in PnR. Timing is one of them. Area could be another.
  12. L

    How to analyse a circuit with multiple feedback loops?

    There is no easy way out of this. Don't make a circuit with so many loops. Can you share what you're trying to do. We could suggest alternate ways to get there.
  13. L

    What is this circuit used for?

    VEry interesing. It does work as a low gain stage. Is it being used as a sort of a level shifter. Did you ever simulate it vs using pmos and seeing the difference.
  14. L

    Datasheet maximum ratings

    Doesn't datasheet specify the maximum Id itself. Why do you need to calculate it. Remember they pulse the Id when they specify it (as far as I remember) to allow heat to dissipate.

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