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Recent content by love2read

  1. L

    power consumption of digital systems

    Do we need to generate test vectors Prime Power to work?
  2. L

    What does fault coverage refers to?

    FAULT COVERAGE The fault coverage rate gives you the estimate that the bad die you can detect from production test on ATE machine.
  3. L

    What exactly is a pulse sync?

    Anyone?
  4. L

    DC question about "set_dont_touch" command

    DC question You are misunderstand "set_dont_touch" with "set_dont_use". "set_dont_touch" is some hard mirco or clock you don't want synthesis tool to change it. "set_dont_use" is not to use certain cells.
  5. L

    Hold time violation question?

    You have to put clock skew into your mind in order to understand what is Hold time violation. Your data path may be shorter than your clock skew to make hold time violation happens.
  6. L

    When do we need to double clock the signal before presenting it to a state machine?

    Doubt in digital signal came from different clock domain.
  7. L

    How to write Synthesis scripts?

    Synthesis scripts read library read files set clock set delays compile out netlist check reports
  8. L

    What's the best Verilog simulation software?

    verilog software ncverilog is good
  9. L

    General Tips of reading Verilog Code

    Verdi is a very good tool for read verilog code
  10. L

    USB Host to Host Communication

    USB 2.0 OTG can do that.
  11. L

    Where to start?PT or DC?

    Learn DC first then PT
  12. L

    NC-Verilog post-simulation problem

    ncelab: *e,cuvmur: instance check your library link
  13. L

    NAND or NOR is faster

    NAND is faster
  14. L

    when a Z input to DFF , what output of DFF?

    depends on your simulator
  15. L

    Is it necessary to do post layout simulation after STA?

    Uou can use Verplex to compare the netlist before and after layout, if no error found a STA pass would be goo enough, but make sure your constraint file is good enough including chip boundary.
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