when a Z input to DFF , what output of DFF?

[stormwolf]

hello , when i do gate simulation , and i found a question . A pin input a high-Z to a DFF , and the DFF output a X to the next circuit. But I think the model of DFF is wrong , and i think that when a DFF input a high-Z the output should be 0.
How do you think?

 

[newcpu]

The output will be "X". It is the right result. The DFF model is OK.

 

[salma ali bakr]

u mean by X unknown or don't care ???

 

[ray123]

I just checked my simulation, and the output is "X".

 

[flypig]

simly exam:
high-Z is between '1" and "0",
the gate only take the "1" or "0" as valid input,
so it don't know what to do, so the output is ,"unknown", x statement.

 

[funster]

In real circuits, the output may be 0 or 1, so the model is absolutely correct.

actually if we input a Z to a inverter, the output also should be X.

best regards

hello , when i do gate simulation , and i found a question . A pin input a high-Z to a DFF , and the DFF output a X to the next circuit. But I think the model of DFF is wrong , and i think that when a DFF input a high-Z the output should be 0.
How do you think?

 

[salma ali bakr]

so this means it's unknown
i'm a bit confused now between unknown and don't care
are they the same
or don't cares are only for karnough maps and boolean algebra in general
while unknown shows only in simulation results

 

[leeenghan]

Hi,

Please don't send an "Z" to a FF when the clock is running!

Regards,
Eng Han

 

[tnguyens]

If the FF model is correct. I think you need a good initialization in your simulation setup so that after POR, all of the internal signals are in know states.

tnguyens

 

[love2read]

depends on your simulator

 

[gogogo]

the model is right.
when you input a "z" to dff, in general the model should output "x".
your design should avoid this case, that means you should give all the input of dffs in your design a certain value.
especially, take care about the memory output to your logic when it has not bus holder,

 

[rajesh9999]

The simulator looks at UDP (in case of verilog) or VITAL model (in case of vhdl) of the D Flip flops in the simulation models of the library (for example .sim file of the library vendor's library). It just goes by what model says. The UDP or VITAL models are the ultimate judge. Hope it clears the doubts about Z ..etc.

 

[laglead]

The model is right.

 

[gaonkc]

DFF is consists of sub-device such as nand, inveter etc. If the input of these device is high-z, the output
will be "x" state.

 

[cfriend]

you can open the verilog lib, maybe get the answer.

 

[tukken]

model is ok.

 

[hxnudt]

model is ok, in real circuit the output is 0 or 1 unless metastability

 

[yln2k2]

Hi ,

Model behaviour is correct .

Let me understand the problem .

Possibility to I/P of a FLop to be 'z' is if it is floating ?
or it don't have any driver in current simulation cycle or pads o/p in 'Z' state .

so in the above cases your logic should not effect based on the flop out which is simulated as 'x' .


Thanks & Regards
yln

 

[jjww110]

in real circuit, there is no z, only 0 and 1, in simulation tool, the result maybe dedend on tools!

 

[darylz]

you can find the behavior description in the source file