Hold time violation question?

[dspti]

Hi all,

One question: if there's one hold time violation, what's happened on the output waveform?

If setup time violated, output of register will be delayed one cycle. i'm confused by this hold violation..

See my attached waveform!

 

[satya_422]

Hi,
How ur guaranteed that ur getting the data in the next clock..
Its not always true whether ur getting the data or not..that depends on the data stability..

Voilation is sane for both the setup and holds..
Please revert if ami wrong

--satya

 

[dspti]

Hi satya,

So what you mean both of these two kinds of vioaltion are the same results -- output signal unstable... sometimes delayed sometimes not.

But if i want to measure this setup time and hold time on the tester,
Pattern passed firstly, then i'll shift the input data edge close to the clock sample edge until pattern failed.. then i measured these two edges got the setup time parameter..

Question is how can i expect the failed condition, if you said this ouput is unstable when Setup or Hold time violated..

 

[satyakumar]

Hi

In both cases it will go into matastable state, as u defined in the wave form like output staying in the high state even after it voilated the setup and hold time.
Generally it won't happen either output may go into high state or low state after some resolving time, this resolving time depends on many factors like on technology aswell as input signal rise time. So, it is undefined until next clock edge arrives. But there is a differance interms of solving setup and hold time voilations,
if setup time is voilated then u need to reduce either combinational delay or increasing the slack by adjusting clock period, where as hold time can be fixed by advancing the clock or delaying the datapath signal with respect to clock edge. this hold time problems can be fixed even after layout but setup time is not like that.

If you have further doubts keep posting.

Thanks

 

[dspti]

Maybe it's not clear of this question,

I need to find out the violated condition of setup & hold time.
But i found these two conditions maybe the same results,

I shift the input data edge close to the clock sample edge till failed condition met.
then i measured the timing. -> assuming that this is the setup time.

After that i shift the input data edge in opposite direction close to clock edge till failed condition met, then i measured the timing. --> this is the hold time.

If these two failed conditions are same or not?

Added after 18 minutes:

Hi all,

Here's the detailed description of this question?

Could you tell me the exact output waveform of these two situation?

Thanks,
dspti

 

[satyakumar]

I think the output will evaluate to corect logic level but the resolving time increases. This can be understood from the charectristic curve of invertor.
The resolving time makes increased raise time of output.

 

[satya_422]

Hi,
I can explain one thing Ur shifting data to voilate the setup and hold conditions,

But I am not sure abt clock period , If it is more then after voilation also the output will reach to some stable state we cant expect it either it may be low or High.

There is no specific stable state for setup or hold voilation..

I think u cant msure setup/hold voilation by h/w simulation until u see the excat sampling w.r.t clock.

But in Gate level simulation it will gives the excact voilation by how much time for both voilations..
Dont confuse think for a while..

--Satya

 

[dspti]

Hi Satya,

It's a real case met in my work, but i can't understand so well about this..

The truth is the clock period is very bigger than the setup&Hold timing.
When i measured this timing on the tester with real chip...
It must be Low or High.. but not be "unstable" ---

Let's example with Setup timing,
Assuming that these two pins timing is smaller than 3.5ns , then pattern always failed .. Because i expected the value is 'H' but actual value is 'L'...

if it's OK, then i can say when the setup timing violated the output will be delayed one cycle. The same for hold time..

I'm confused a lot ...

Thanks

 

[love2read]

You have to put clock skew into your mind in order to understand what is Hold time violation. Your data path may be shorter than your clock skew to make hold time violation happens.

 

[satya_422]

hi,
For setup voilation ur telling that getting data in the next clock..
It means by next clock the data may be settling at one stage..
The setup time deals with the capturing flop with next clock edge ..

In case of HOLD Its at Capturing Flop w.r.t.presnt clock..

So it means U may not guess the outcome of HOLD voilation..


--Satya