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I am running OVM env together with some behavior model descripted in verilog.
But seems it is never working....
assign #0.2ns A = B;
But below is OK (changed to always)
always @ * A <= #0.2ns B;
Since another env without OVM is OK, so i doubt it is related with OVM or some delay mode setting.
Thanks! !
And more questions about interface:
1. Can such 2d interface array as a port?
2. How can I use modport in that case if Q1 is OK?
3. for example:
module axi_slave(
my_axi_interface axi_master_interface[nr_of_axi_ports-1:0];
clk,
rstn
);
generate
.*...
interface_instantiation ::=
interface_identifier [ parameter_value_assignment ] module_instance { , module_instance } ;
above is interface instantiation syntax, seems multi interfaces (like an interface array) cannot be clarified together, is that ture?
what im looking for is:
axi_interface...
I am not trying to answer your question, and just want to discuss why you ignore overflow? Is any requirement of stream stability? For example, it is acceptable FIFO overflow every 3s (!?). Is that true? Otherwise, it is not make sense to me that in/out ports of FIFO have different data rate..
This is very simple timer logic, power up 500us, reset 200us, and the cke....
If you want to make generic/programmable logic to control such process, you have to write several timers/counter to do it.
hi yhn
I think use some like 'grep' or 'sed' tools for find 'force' keyword in ur design will be more easy.
Btw: if somebody find method to detect forced signal in VCS, please also tell me.
Hi Jean
I think you can't get expected result.
firstly, we need understand what is multicycles: is cant finish in one clock cycle. ForExample: 6cycles.
that's mean you need wait 6-cycles to capture comb result use regB. But before you get this result, you need steady input of comb logic. i.e...
yes, rhythmrain is right. If you only care about fifo work fine, 2-level fifo will be enough.
but your fifo looks like design for HDMI. so it also depend on your application.
ddr3 zq
hi sree205
i think zq calibration in ddr3 is method for improve data & cmd signal integrality.
copy from jedec:
ZQ Calibration command is used to calibrate DRAM Ron & ODT values. DDR3 SDRAM needs longer time to calibrate output driver and on-die termination circuits at...
clock frequency ppm
hi feel_on_on
i think if you meet case that different ppm in write clock and read clock, u have to consider worse case to calculate fifo depth.
littlebu
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