Why Combinational Outputs must not be taken directly?

[hb_cancer]

Hi,
What is the reason that the Outputs of Combinational Logic is not taken directly? Is it because it is independent of Clock? Please enlighten....
Thanks!

 

[littlebu]

Hi hb_cancer

i think the thats for improve timing: give more margin for external logic.

 

[ljxpjpjljx]

yes , the timing should be considered when the logic output!

 

[dechen]

other than improving timing, Combinational output is not safe for the receiving block to do synchronization, a glitch may occur if receiving block synchronizes the combinational logic directly.

 

[vlsichipdesigner]

hi,

my 2 cents,

the reason is to not to have surprise later during timing analysis.

Say you have a module and one of the port is not registered and going out like that, if the path is not well optimized and correctly modelled during your module timing analysis, then this path can open up during the chip level timing closure effort bring your module and your neighbour module to whom you are giving your output data too.

to better understand the concept check the below mentioned link, will give you clear understanding.
https://www.vlsichipdesign.com/static_timing_analysis.html


myprayers,
chip design made easy
https://www.vlsichipdesign.com

 

[nschiku]

HI,
Well its better to register the outputs in order to avoid longer paths which may lead to timing violation.

-Nik

 

[vipulsinha]

Hi

We dont take output as a denominational one as to avoid glitches.. the registered output is always stable..