bradyue
Member level 2
how to determine the depth of this FIFO?
write clock is 40Mhz, read clcok is 50Mhz
data is written into FIFO constantly and repeatly, like 0 1 2 3 0 1 2 3
data is read from FIFO repeatly, lie 0 1 2 3 x 0 1 2 3 x
x means no read.
that means every 4 write clock, data in and out of FIFO are the same.
so, how to determine the depth of this FIFO, and how many cycles should data write be ahead of data read?
write clock is 40Mhz, read clcok is 50Mhz
data is written into FIFO constantly and repeatly, like 0 1 2 3 0 1 2 3
data is read from FIFO repeatly, lie 0 1 2 3 x 0 1 2 3 x
x means no read.
that means every 4 write clock, data in and out of FIFO are the same.
so, how to determine the depth of this FIFO, and how many cycles should data write be ahead of data read?