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There are two in googlel code :
cu-hw-gps - Cornell University Hardware GPS Receiver Project - Google Project Hosting
ece3710-gps-module - Simple GPS module - Google Project Hosting
Hope this would help.
I don't think I get your information correctly, but here is what I think :
The frequency for FFT calculation can be totally different with the sample frequency as long as you
registered all the gps data. Cause usually FFT take several iterations to finish, you can not run it during
reading gps...
sorry for my poor expression.
My question is on how to talk to the testbench from a program that is running on a simulated CPU. Like when you want to test your GPIO pins, you might want control the external stimulus on the pin from within the program.
thanks
Dear All :
I'm verifying a SoC with a 8051 IP core . And during the top level verification , I'm confused about how to co-verify with hardware and software !
For example, I want to test the gpio function . Then I wrote the test program . But I need to drive the stimulus to my SoC after the...
verilof fwrite
Dear all :
I'm using $fwrite to write a binary file in vcs simulation enviorment.
$fwrite(fd,"%c%c%c",8'H42,8'H4D,8'H00);
but the output file come out to be : 0x42 , 0x4D, 0x20 ;
why I can not write 0x00 to a binary file using $fwrite in VCS enviorment ???
It's...
Dear all :
Someone tell me that vcs or ncverilog could read in synopsys lib or db timing information without using a sdf file .
Is that true ?
If it's true , how could I read in these file ? which option should i use ?
thanks
mbist 4 dual port ram
in test_ram.v :
u define word_depth as 576 (0x240)
but ur address range is 0 to 1023 .
as a result the max address u can write is 575 , then in the simulation waveform , u will find no output after address 575(0x23F) .
Added after 17 minutes:
I changed 576 to 1023 in...
Dear All :
I used to think that for prelayout gate level netlist , we can use nospecify and notimingcheck option to run simulation to verify wihtout sdf annotated . But I used these two option for both ncverilog and vcs , and result turn out to be different . Ncverilog failed while vcs...
mbist 4 dual port ram
Hi holysaint
There might be lots of possibilities .
Maybe the memory model is not correct .
Maybe the simulation options are not set correctly.
I will go check the spot where fail_h go high . If the memory output is X , there might be timing violations .
mbist 4 dual port ram
Hi holysaint
It seem realy weird that test_QA go to X suddenly when reading the address 0xB70 . Have you checked that certain value was written int o 0xB70 before this ?
scheduled event for delayed signal
Dear all :
I'm running ncverilog with sdf annotated . Than the following message came up :
Scheduled event for delayed signal of net "D" at time xxxx PS was canceld
File: xxx/xxx/xxx/std.v , line = 8569 ;
Scope test.u0.xxx.xxxx
Time : xxxx PS
What...
mbist
Deal all :
I'm using MBistArchitect to insert bist logic for a design with about 100 memories in it . I'm going to implement a bist controller for the memories in the same hierarchy , and each bist controller has a fail_h and a tst_done signal . Then in top level , there are many...
from my understand, rc extracted from cap table is not as accurate as that extracted by fire&ice .
but it takes much longer time using fire&ice .
so u may use cap table & scaling factor to calculate rc in the p&r stage .
but u'd better use fire&ice or other sign-off tools to extract rc after p&r .
Hi all,
I'm using Mbistarchitect to generate bist for rom . I'm confuse that whether
should I write the address scrambling definition in the rom model .
I tried to write that in the rom model but the simulation failed . And I found the
signature was the same.
thanks
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