Mbist insertion issue.How should I handle these fail_h sig?

[leeguoxian]

mbist

Deal all :

I'm using MBistArchitect to insert bist logic for a design with about 100 memories in it . I'm going to implement a bist controller for the memories in the same hierarchy , and each bist controller has a fail_h and a tst_done signal . Then in top level , there are many fail_h and tst_done signals .

How should I handle these fail_h and tst_done signals ?

thanks

 

[papertiger]

Mbist insertion issue

use a bist for all memories. or
AND lgoic all fail_h and tst_done.

 

[HolySaint]

Mbist insertion issue

a ctrl for more mems can solve this problem

 

[sunilbudumuru]

Mbist insertion issue

Hello Friend,

To Distinguish which RAM has a failure, We can implement using a seperate fail_h for each RAM or a single fail_h.
To Distinguish which RAM testing is done , We can implement using a seperate tst_done for each RAM or a single tst_done.

Single fail_h : With single fail_h, RAM testing is done sequentially. Scan_out pattern includes memnum(Number of memory failing), address of the failing location and failing data. Single fail_h testing takes more number of clocks for memory testing.

Seperate fail_h : With separate fail_h, RAM testing is done in parallel. We can know which RAM is failing by monitoring the fail_h signal. We can get the failing data through scan_out. Separate fail_h testing takes less number of clocks for memory testing.
But we need more pad's to multiplex the extra fail_h signals.

Same is applicable for the "tst_done" signal.

If u r more concern about the area overhead, use single fail_h/tst_done signals for all the RAMs (there is an option in the MBISArchitest). But here u need to sacrifice the test time which takes more time as testing of all the memories will be sequential.

The second option is generating the seperate fail_h/tst_done signals for each RAMs and provice that many number scan_out, fail_h, tst_done ports (or U CAN MULTIPLEX these seperate "fail_h/tst_done" signals with toplevel ports, if u dont have that many ports). In this case u can save testing time but it increases the area overhead.

Hope this info helps you.

Rehards,
Sunil Budumuru[/b]

 

[HolySaint]

Mbist insertion issue

when i insert the bist output to my design
i find error : the fail_h went high?

why?

i test the ctrl and the con model well

 

[sunilbudumuru]

Mbist insertion issue

Hello Friend,

The fail_h signal goes high at the first occurrence of a miscompare. It remains high for the remainder of the test.

1. So set a $display for the fail_h signal at which it is asserted (miscompared). Check if it is during the initial phase of the simulation or at the later stage of the simulation.

2. Generate debugz signal for your controller for the purpose of debug where it miscompare has been done.
Debug Mode (debugz = 1 ) When debugz is set to 1 , the diagnostic mode is enabled. In this mode, a miscompare will suspend the operation of the BIST controller, and the failing data will be serially scanned out of the controller through scan_out. Once the failing data has been scanned out, the BIST controller will resume the test. The scan out operation will repeat on every occurrence of a miscompare.
(from MBIST GUIDE from Mentor)

On the bottom line, be sure to find the culprit for the assertion of fail_h signal. My suggestion is use option1 and lokinto the simulation results. Then go to option2. In option 2, u need to have one more extra port for debug (debugz).

Good Luck.
Please update us once u r done.

Regards,
Sunil Budumuru.