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Recent content by lagos.jl

  1. lagos.jl

    Signaling used in System-on-a-Package

    Thanks for the reply kishore2k4! Hum, I am afraid I messed up my question a little... Doing a little further reading I have realized that SoP and SiP (System-in-a-Package) might not be the same. I guess SiP is more related to the VERTICAL stacking of different dies, while SoP is more like bare...
  2. lagos.jl

    Signaling used in System-on-a-Package

    Hi all! Could anybody please tell which signaling schemes are commonly used for implementing the (parallel) data buses in a System-on-a-Package (SoP)? I mean, how is the communication between cores in the various silicon dies that make the SoP accomplished? ...from what I have seen so far it...
  3. lagos.jl

    Ringing between power clamp and package parasitics

    Thanks a lot for the reply, Humber. In my case, modeling the switching noise -whether it be of oscillating nature or not- is one of the main goals. Would it make sense to model the entire system in Cadence using perhaps a Spice model of a real voltage regulator, in order to take into account...
  4. lagos.jl

    Ringing between power clamp and package parasitics

    Hi all; I still haven't been able to figure out this one... any help is welcome and really appreciated :) Regards, Jorge.
  5. lagos.jl

    Ringing between power clamp and package parasitics

    Hi aryajur & FvM! ...After experimenting a little with the circuit I've come to some results; I would be really grateful if you could please give me further advise. I checked the data relative to the package I am considering, and found that Rpackage+Rwirebond should be approximately 0.1ohm...
  6. lagos.jl

    Ringing between power clamp and package parasitics

    Hi Aryajur! thanks so much for your reply. What could be a typical value of the series resistor that I could add in order to model the resistance of the loop and avoid the oscillations? Or even better, do you know of any reference (book, paper, etc.) that deals with this "problem"? Thanks...
  7. lagos.jl

    Ringing between power clamp and package parasitics

    how to avoid ringing due to bond wire models Hi all! I am having problems trying to simulate a very simple circuit; I hope someone can give me a hint on what's going wrong. Basically, the (equivalent capacitance of the) ESD power clamp protecting my chip is oscillating with the parasitic...
  8. lagos.jl

    Typical substrate contact resistance values?

    typical contact resistances llbaobao, thanks so much for your reply. In my case I am still in design phase so don't have any layout to perform parasitic extraction. However, I was advised to use a 100 to 200 ohm resistor in series with the bulk terminal of every transistor to model this...
  9. lagos.jl

    Typical substrate contact resistance values?

    typical resistance values Dear all, What is a typical value for the resistance of the substrate connection of each MOS in a 0.35 CMOS process? I am talking about the effective resistance that, for instance, the bulk terminal of an NMOS will see to the ground line, when directly connected to it...
  10. lagos.jl

    How to select and plot individual results of parametric sim

    cmos53.scs Hi all!. After reading the related Cadence documentation and searching through the web I haven't been able to figure out the Skill /Ocean code needed to 'grab' and plot individual results from a parametric analysis. Please consider the following sample code: ...
  11. lagos.jl

    Literature on guard rings

    Thanks for the reply! Hastings' treatment is good but kind of brief, and doesn't give much examples or practical tips. Do you know of any other references with more examples/practical considerations, like for instance: -Which types of blocks need to be protected with rings and which don't...
  12. lagos.jl

    What are the guard rings ?

    Re: guard rings Thanks for the references. Hastings' treatment is good but kind of brief, and doesn't give much examples or practical considerations. ...Maybe there are any other references with more examples/practical considerations, like for instance: -Which types of blocks need to be...
  13. lagos.jl

    Literature on guard rings

    Hi all! Is there any existing formal literature dealing with the topic of guard rings? I have made a preliminary search on the net and I was unable to find a single reference on the theory behind the design and operation of these by-no-means-trivial though extremely important IC elements. All I...
  14. lagos.jl

    What are the guard rings ?

    Re: guard rings Hi all! Is it out there any existing literature dealing with the topic of guard rings? I have made a preliminary search on the net and I was unable to find a single reference on the theory behind the design and operation of these by-no-means-trivial though extremely important...
  15. lagos.jl

    POLL: Best schools on RFICs/MMICs in US & Europe

    Re: Best schools for MSc/PhD on RFICs/MMICs in US & Euro Hum, very interesting! So the conclusion would then be that (at least from the academic/research point of view) there is really no good reason to go to US institutions, if one can obtain the same level of education (or even better) and...

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