Signaling used in System-on-a-Package

[lagos.jl]

Hi all!

Could anybody please tell which signaling schemes are commonly used for implementing the (parallel) data buses in a System-on-a-Package (SoP)? I mean, how is the communication between cores in the various silicon dies that make the SoP accomplished?

...from what I have seen so far it seems that up to the Systems-on-a-Chip (SoCs) the traditional parallel bus (with repeaters) was still used for communicating between the various cores. Is this approach still used in SoPs?

Any comments/references/links are welcome! Thanks in advance!

 

[kishore2k4]

AFAIK, SoP doesn't need to use anything different from the conventional chip to chip signalling. The primary advantage being significantly reduced path capacitance(low power, high speed, better SI etc), the routing is also simulated and tested by the designer itself, leaving less critical paths to be routed off-package and still garuantee the specifications. They are mainly used to integrate memory(flash,dram) with computing(CPU) in size/power constrianted devices like mobile phones/handhelds etc.

SoP is a "technical" term for PCB with bare dies in a single package.

SoCs on the other hand are increasingly using onChip Interconnect topologies that are easy to scale both with chip complexity and as well as process nodes.

 

[lagos.jl]

Thanks for the reply kishore2k4!

Hum, I am afraid I messed up my question a little... Doing a little further reading I have realized that SoP and SiP (System-in-a-Package) might not be the same. I guess SiP is more related to the VERTICAL stacking of different dies, while SoP is more like bare dies in single package (as you say), but not necessarily stacked and interconnected in more traditional ways.

Taking into account this subtle difference, I believe that I am really interested in the die interconnections within SiPs, and more precisely, on how the data buses are implemented within cores residing on different dies.

Could you please comment further on this topic? Thanks in advance for any help!.

 

[kishore2k4]

You are right about the difference between SoP and SiP. The current trend is SiP followed by 3D interconnects where connections go through the dies.

The most common application for SiP is place/power/size constraints and SI/EMC issues in high frequency chips. I am not sure what level of detail you are expecting from this post, maybe you can ask a more specific question.

The dies are usally made to fit in normal packaging and when the application demands they are all placed in a single package. There is no need to design special buses for such applications as interconnects are very short in length and the substrate of the package can route multiple layers with very small feature lengths providing a very high density interconnect.

The following document should give you a good overview of what SiP is and what it looks like internally.
**broken link removed**

Amkor is a company that specialises in all things IC packaging. You should check them out.