Typical substrate contact resistance values?

[lagos.jl]

typical resistance values

Dear all,

What is a typical value for the resistance of the substrate connection of each MOS in a 0.35 CMOS process? I am talking about the effective resistance that, for instance, the bulk terminal of an NMOS will see to the ground line, when directly connected to it (like the typical NMOS with source and bulk tied to ground that are found in simple current mirrors). I believe this resistance should take into account the bulk resistance as well as the contact and vias resistance as well.

I've noticed that the BSIM3v3 model does not model this resistance, but I am working in a very sensitive design and need to model this resistance accurately. I plan to model it by adding in my schematics a resistor in series with each transistor's bulk terminal, both for PMOS and NMOS.

Well, thanks in advance for any information/ideas/references!

Regards,

Jorge.

 

[llbaobao]

typical contact resistance

You may hardly get the exactly value of the parasitic resistance of the bulk terminal.
Commonly we use the p-sub wafer, ρ≈13Ω•cm(or around 10Ω•cm),
if use an epi-sub wafer,ρ≈0.01~0.1Ω•cm
R=ρ*L/S=ρ*L/(w*h)=(ρ/h)*(L/w)=Rsquare*L/W
h is the hight of the resistance, is nearly a constant.
For the bulk is a whole one, and it have many recursive path to the ground PAD( or sub PAD),so one can hardly give out the accurate parasitic resistance.

Use the LPE,we can get a coarse vaule of it.

 

[lagos.jl]

typical contact resistances

llbaobao, thanks so much for your reply. In my case I am still in design phase so don't have any layout to perform parasitic extraction. However, I was advised to use a 100 to 200 ohm resistor in series with the bulk terminal of every transistor to model this resistance... do you think it is an appropriate, realistic range of values?

thanks again for your advice,

Regards,
Jorge.

 

[fredflinstone]

6-10 ohms per contact is a realistic number