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Thats what..automatic is for reentrant tasks & recursive functions..(as far I know)
but this is a reentrant funciton..Some books are telling to use automatic in reentrant functions also.
But in their example they give recursive examples.
What I want is a synthesizable code with above example...
Thanks man,but I don' think you got the question.
suppose parity() is a function,
and If I write
assign a = parity(A);
assign b = parity(B);
and if I want it to be synthesized ,
do I need to add "automatic" in function declaration ??
Hii all,
I have a function to implement & call it in parallel 5 times. So it has to perform 5 parallel calculations.
& The code needs to be synthesizable.:razz:
I am having doubt on "automatic" functions,they are mentioned in some tutorial websites to be used in case of recursive functions.
And...
Hi people,
can you suggest any good color scheme for verilog coding :lol: ,with good syntax highlighting & dark background.
I am currently using the inbuilt elford ,but its straining my eyes a little.
& if possible for C also.:-?
Hi sudha,
Isnt it correct that the same thing can be done via normal access.(read-modify-write back).
Why there is this dedicated functionaly and what it is offering over the normal (read-modify-write back) access.
Hi all,
I am trying some to take out some `defines from a main.v file and put them in a seperate delay.v file.
Now there are 2 ways of doing this,
if I dont `include that in main.v file,and give delay.v in filelist.f of compilation.
If I include that file then I can not/ should not give that...
Hi yx.yang
any idea what it will synthesize ? I mean what algo will be used in compilers for synthesis.
---------- Post added at 09:55 ---------- Previous post was at 09:43 ----------
Hi yadavvlsi,
I was reading this article & found it is a clock divider circuit,if I am not wrong.
I am sorry...
it is advised not to write casez or casex for to-be-synthesized code as it may show non-parallel property & leading to a priority mux structure while synthesized..
which may not be what you are intended to.
Hi all,
I want a circuit which will combinationally divide a number by 3.(or in one cycle :idea:)
whats is given is that number will always be divisible by 3 only.:razz:
post any tutorial link or any helpful post..as I couldnt find any moderate one.
Is it necessary to have a synchronizer after a multicycle path ?
Isnt it the receiving flop can become metastable at any cycle between initial & last cycle?8-O:-?
I think the example which you have given here for sub-design isnt a MCP case,
MCP is nothing but tool (sta / synth) will give that path 2 cycles for checking violations.
but here you are enabling flops after multiple cycles of the master clock,for driving them with effectively lower frequency.
Re: career in wipro vlsi
what do you want isnt clear..
as per your statement you got wipro vlsi & wipro software.
you have to choose between them,you cant go in software & later join vlsi.
its 2 different domains there. :X :X
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