problem with `include in verilog

[krishanu007]

Hi all,
I am trying some to take out some `defines from a main.v file and put them in a seperate delay.v file.

Now there are 2 ways of doing this,

1. if I dont `include that in main.v file,and give delay.v in filelist.f of compilation.
2. If I include that file then I can not/ should not give that in filelist.f for compilation.

Now I I want to do it in the 1st way which is giving problem that definition not found..
please help !!

 

[dave_59]

This should have worked in Verilog, but in SystemVerilog, definitions from `defines in one file don't necessarily carry over to the next file, depending on which tools you are using.
2nd way is preferred and you should write your delay.v file like this

`ifndef DELAY_V
`define DELAY_V

// body of delay file

`endif

That way your defines only happen if they have not been defined already.