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Re: DFF without reset ?
Hi,
My experience is using DFFs with or without reset doesn't really matters. During
powerup, most FFs will have a know logic 0 or 1. But you have to know before hand
the uncontrollable output will cause any undesire effect or not.
For DFF with async reset, we can...
Re: mmu design help
Reading from eeprom is straight forward. However, the erase & program will take quite a long time and post serious performance impact on your chip if your CPU has to wait until the erase/program finishes.
My suggestion is to do simple read, but add data buffer for eeprom...
Another way you can think of is to use a Schmitt-trigger input pad with pullup (active-low reset, 5~10kohm). This can reduce the chance that board-level noise injected into reset pin.
tsmc pad
Hi,
As I remembered:
PVDD1SDG - VDD pad for Core and connected to VDD(or GND) in LVS netlist
PVSS1SDG - VSS pad for Core and connected to VSS in LVS netlist
PVDD2SDG - VDD pad for IO and connected to VDDPST in LVS netlist
PVSS2SDG - VSS pad for IO and connected to VSSPST in LVS...
ucf setting constraints skew
If you are using FPGA such as Xilinx' Virtex 4 family, there are clock MUXes to perform clock switching.
However, if you are unlucky that your ASIC library do not have clock MUXes, you may need to use manual resizing to make your MUX have higher drive and perform...
scan chain asic
Triggering clock pulse between scan shift is usually appeared in capture cycle. In which the injected test pattern has been applied to internal combo. logic. An extra clock pulse (capture clock) is used to latch the internal combo. output to scan FF and then shift out for...
Here are my suggestions:
1. Sample & detect the falling edge of ALE and latch P0 & P2 for the address upper and lower address.
2. Detect the fallowing of P3[6] and P3[7] for read & write operation with the address latched during ALE being asserted. You should have so much time to do I/O with...
My opinion is you should try to read some books & example codes for design reuse & DFT. This is very vital when you've to work with your colleagues and know how to write good code to be able to being debug and and can be integrated with others' module.
ASIC design is team work, managible code &...
Re: ATPG
To wkong_zhu:
You're so unlucky that your test mode pins has to be shared with normal I/O. I know the pain on defining the init. test protocol in this situation...
My suggestion is to use dedicated I/O for these test pins...
To zzy_zy:
ATPG is very important. You can think of a 16bit...
Re: ATPG
My opinion is FE design should bare DFT in their mind during design.
It's because a design with DFT violation needs huge effort to fix it for ATPG especially the FE designer don't want to modify their freezed design(I'm a FE designer but seeing so many colleagues have DFT ignorance...
+notimingcheck
Of course. If you use +notimingcheck option, when there are setup/hold/timing
happened in your FF, you will not got an "X" (notifier assertion in gate level verilog
library) and warning messages.
My opinion is you should better use +no_notifier instead, which will report...
Re: The "unknown status" can cause a "lock st
Another point is in real chip, power-on-reset has to be taken care. It is always a good practice that external master reset is present. If the on-chip POR is not working , you can connect your external master reset with some RC or power on...
sdf annotation cell not found in netlist
Hi,
It's one common problem encountered in SDF annotation. It is caused by different timing arcs defined between syn. & P&R libraries. I know that some library vendors do provide some scripts (perl or tcl) to translate the post P&R SDF to the format...
v2lvs can translate verilog netlist into spice netlist. However it also creates a pinmap attribute which may not be supported by some spice simulator.
Another approach is to use Cadence Virtruso Composer to do the netlist translation. But it is not very user friendly(You've to read in the cell...
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