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puzzles about spice in Standard Cell Based Design?

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patriot

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my design is Standard Cell Based Design,i use verilog for Behavior Description,and logic synthesise with DC,but how can i get the spice netlist after synthesis?
is it to use spice to design cells ? then synthesis based these cells?

i am confused with the design flow?
thanks for help
 

It is not common to do spice simulation for digital design. You may need it for cell design. Now you need to do timinig verification.
 

The Library vendor provides the spice-netlist for each cell. But you still need some netlist translator to translate the synthesized gate-level netlist to spice-format netlist for transistor-level simulation.
 

sunjimmy said:
The Library vendor provides the spice-netlist for each cell. But you still need some netlist translator to translate the synthesized gate-level netlist to spice-format netlist for transistor-level simulation.
hello. what is the fomat of the file that the vendor provide?And how do you translate that? thanks
 

maybe v2lvs in calibre will help you
 

tukken said:
maybe v2lvs in calibre will help you

but v2lvs is to translate the netlist after P&R to SPICE-format
which tool can translte the gate-leval netlist to spice-format netlist?

thanks!
 

v2lvs can translate verilog netlist into spice netlist. However it also creates a pinmap attribute which may not be supported by some spice simulator.

Another approach is to use Cadence Virtruso Composer to do the netlist translation. But it is not very user friendly(You've to read in the cell library and do some pin order mapping job first).
 

kctang said:
v2lvs can translate verilog netlist into spice netlist. However it also creates a pinmap attribute which may not be supported by some spice simulator.

Another approach is to use Cadence Virtruso Composer to do the netlist translation. But it is not very user friendly(You've to read in the cell library and do some pin order mapping job first).

is there some synopsys tool for netlist translation? gate——>spice
 

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