patriot
Member level 5
my design is Standard Cell Based Design,i use verilog for Behavior Description,and logic synthesise with DC,but how can i get the spice netlist after synthesis?
is it to use spice to design cells ? then synthesis based these cells?
i am confused with the design flow?
thanks for help
is it to use spice to design cells ? then synthesis based these cells?
i am confused with the design flow?
thanks for help