reduce skew for clock pass through mux

[skyworld]

muxed clock skew balancing

in my project two clocks passing one mux. i checked the results and found that there are big delay after these clocks passing through the mux. so FFs after that can't capture data correct because data can't align the clock. Do any body know how to deal with this? can it be fixed through metal fix , or re-synthesis or re-P&R? can i test it within FPGA? thanks



skyworld

 

[kctang]

ucf setting constraints skew

If you are using FPGA such as Xilinx' Virtex 4 family, there are clock MUXes to perform clock switching.

However, if you are unlucky that your ASIC library do not have clock MUXes, you may need to use manual resizing to make your MUX have higher drive and perform clock tree synthesis.

Be sure that you have to resolve clock convergence issue so that clock tree can punch through the MUX.

 

[omid219]

reduce skew bufgmux

In FPGA, you have to force the place & route tool to connect the multiplexer's output to dedicated clock path (for example BUFG in Xilinx). Sometimes, you may need to edit the synthesized netlist to do this. But do it carefully.

In Asic, you have to define the multiplexer's output as clock root and generate clock tree based on it.

 

[skyworld]

ucf clock insertion delay

Hi all,
thanks for your help. but i still have the question: define the clock after mux as a root and make a clock tree is ok, but before i do this, this clock after mux has a large skew, it is delayed so that data can't align with clock. in this case, will defining it as root and making a new clock tree work? i have tried this in vertex-e 8000 fpga, it doesn't work. i guess maybe i should insert some buffer into data bus, but the data bus is 32 bit and i don't know how many buffer should i insert so that the timing could be ok.

 

[omid219]

ucf skew=

Have you tried using BUFG after mux? As I saied before you can insert a BUFG immediately after mux. The output of BUFG is connected directly to dedicated clock path in FPGA (Xilinx). You can edit the netlist and add this buffer manually.

 

[skyworld]

bufgmux constraints

yes, i have inserted bufg and i have tried bufgmux, all is useless

 

[omid219]

reasons to reduce skew

How much is the clock frequency? I've faced this issue for 50 MHz design and could fixed it with BUFG. The only thing that I can say is to add some constraints in UCF file to force P&R tool for better timing optimization for those paths and increase the effort level of p&r tool.

 

[skyworld]

xilinx clock mux

that sounds good! can you tell me how to set these contrains in the ucf file? i am not fimiliar to thse. thanks. by the way, the clocks are 27MHz and 100kHz.

 

[Nobody]

mux clock tree synthesis

You can add the dummy bufgmux to balance the source data's clock .
BUFGMUX dataclk(.O(data_clk), .I0(root_clk), .I1(1'b0), .S(1'b0));
Otherwise you have to switch to negedge clock for safe capture .

 

[Thomson]

muxing of two clocks

I took this method to implement the muxes to moderate the difference existing the two clocks:
(1) first set a reasonable values to one of the clock including the clock period and the skews and insertion delay
(2) then set the other clock source using the ones created by the step1

if the step2 cannot create a valid clock network, then you can take the average value between the step1 and step2, and try again.

Using this method, i finally got a reasonable clock network.

 

[omid219]

xilinx reducing clock path skew

You can define different timing constraints on special nets in UCF file. You can see a piece of
my UCF file in below. Try these kind of contraints too.

TIMESPEC "TS_XCLK" = PERIOD "clk_50M" 20.0 ns ;
NET "top/clk_25M" USELOWSKEWLINES ;
NET "top/Q1" MAXDELAY= 6 ns;
NET "top/U231/t10" MAXSKEW= 1 ns;

Hope it help you.

 

[skyworld]

ucf cannot dedicated clock

thanks. i will try these methods.