Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by kaiser

  1. K

    Help me convert VHDL code to Verilog

    Re: convert from VHDL The goal of this sorce code is to write "PACE" on the seven-segment LED display on the Spartan3 board (starter kit from Xilinx) Since seven-segment LED displays are timed multiplexed, I will need "something" to tell me to write the first character, then something which...
  2. K

    Help me convert VHDL code to Verilog

    Some one help me with this code in VHDL .....i want to cnvert this code in a verilog code and i dont know how....HEELLLPPP This is the code in VHDL: entity vhdlmodule is Port ( CLKIN : in std_logic; AN3 : inout std_logic; AN2 : inout std_logic; AN1 : inout...
  3. K

    Help me jump over counter values in a code

    module CONTROL( ld, clk_c, rst_c); output [3:0] ld; input clk_c; input rst_c; reg [3:0] ld; reg [2:0] count; always @ (posedge clk_c or posedge rst_c) begin if (rst_c) begin count<= 3'd0; ld <= 4'b0; end else begin count <= count +1 ; case (count)...
  4. K

    Free Lattice Reference PCI Target 32-bit/33MHz Core

    The PCI Target from Lattice is very good....no errors found by me.... I used this PCI target within a project....and when I put the source codes in my FPGA (Altera Cyclone II) it works fain with a motherboard which had a 3.3V and 5V on PCI BUS.... Try it!..It is very cool.. If you want more...
  5. K

    Verilog codes for clock divider

    Re: CLK Divider HELP Thank you very much.... it was helpfully.. After i was looking over your suggestions, i made this(from 50Mhz downto 1Hz with 50% dutty cycle) module clk_div ( clk_in, reset,clk_1hz); input clk_in, reset; output clk_1hz; reg clk_1hz; reg...
  6. K

    Verilog codes for clock divider

    I have a 50 Mhz clock on my board and i need a 60Hz clock for my design...... Somebody can suggest anything to do...? A verilog descripiton it will be very nice....(with comments- general mods) THX IN ADVANCE!!
  7. K

    Help with a start project..

    I'm a relatively beginer in FPGA design.. I know something in Verilog....but i need some advices in my new project... I have a Spartan 3 Starter Kit board....and i want to make a verilog description of a circuitry which command 4 digits on the board. Give me some ideeas how to begin.....i want...
  8. K

    What circuits or methdology is used for frequency multiplier

    Re: frequency multiplier --Serial Multiplier Module-- module mult(clk, load, ain, bin, eb, done); input clk, load; // clock and load/start signal input [31:0] ain, bin; // multiplier and multiplicand of n bits output [63:0] eb; // product of 2n bits output done; // product-ready signal reg...
  9. K

    How to design a barrel shifter using verilog language?

    A barrel shifter has much more functions then a simple shifter. - selects arbitrary contiguous n bits out of 2n input buts. - right shift: data into top, 0 into bottom; - left shift: 0 into top, data into bottom; - rotate: data into top and bottom. Here is an example o simple...
See more

Part and Inventory Search

Back
Top