Help me convert VHDL code to Verilog

kaiser · Jul 14, 2005

Some one help me with this code in VHDL .....i want to cnvert this code in a verilog code and i dont know how....HEELLLPPP

This is the code in VHDL:

Code:

entity vhdlmodule is
    Port ( CLKIN : in std_logic;
           AN3 : inout std_logic;
           AN2 : inout std_logic;
           AN1 : inout std_logic;
           AN0 : inout std_logic;
           LED : out std_logic_vector(6 downto 0));
end vhdlmodule;


architecture Behavioral of vhdlmodule is

signal CTR : STD_LOGIC_VECTOR(12 downto 0);
begin			
  Process (CLKIN)
  begin
    if CLKIN'event and CLKIN = '1' then
      if (CTR="0000000000000") then
        if (AN0='0') then 
          AN0 <= '1';	 
          LED <= "0101011";             
          AN1 <= '0';
        elsif (AN1='0') then 
          AN1 <= '1';	 	 
          LED <= "0101011";             
          AN2 <= '0';
        elsif (AN2='0') then 
          AN2 <= '1';	 
          LED <= "0001000";             
          AN3 <= '0';
        elsif (AN3='0') then 
          AN3 <= '1';
          LED <= "0000110";             
          AN0 <= '0';
        end if;
      end if;
      CTR<=CTR+"0000000000001";
      if (CTR > "1000000000000") then   
        CTR<="0000000000000";
      end if;
    end if; -- CLK'event and CLK = '1' 
  End Process;
End Behavioral

AND HERE IS WHAT I MAKE AND DONT WORK...

Code:

module pace(	CLK,
					AN0,
					AN1,
					AN2,
					AN3,
					LED
				  );
  inout AN0,AN1,AN2,AN3;
  input CLK;
  output [6:0] LED;
  reg [6:0] LED;
   
  reg [12:0] count;

  always @ (posedge CLK) 
  	
			if (count==13'h0)	
				begin
					if (!AN0) begin
						AN0 <= 1'b1;
						LED <= 7'b0010010; // A
						AN1 <= 1'b0;
						end
					 else if (!AN1) begin
						AN1 <= 1'b1;
						LED <= 7'b0110001; // C
						AN2 <= 1'b0;
						end
					else if (!AN2) begin
						AN2 <= 1'b1;
						LED <= 7'b0011000; // P
						AN3 <= 1'b0;
						end
					else if (!AN3) begin
						AN3 <= 1'b1;
						LED <= 7'b0110000; // E
						AN0 <= 0;
				 end
			  count <= count + 13'b1;
			  if (count > 13'h1000) begin
			  	count <= 13'h0;
				end				
			end
endmodule

dBUGGER · Jul 14, 2005

convert from VHDL

Hi kaiser,
please do include a 'begin' after always @posedge
and an end statement at the last before endmodule. Just try that.

Best Regards,

nand_gates · Jul 14, 2005

Re: convert from VHDL

This code looks meaningless! Could you explain what hardware you want to
describe by this code???

Added after 8 minutes:

If you just want the translation then here it goes.....

Code:

module pace(   CLK,
               AN0,
               AN1,
               AN2,
               AN3,
               LED
               );
   inout AN0,AN1,AN2,AN3;
   input CLK;
   output [6:0] LED;
   reg [6:0]   LED;
   
   reg [12:0]  count;
   reg         AN0_r,AN1_r,AN2_r,AN3_r;
   assign      AN0 = AN0_r;
   assign      AN1 = AN1_r;
   assign      AN2 = AN2_r;
   assign      AN3 = AN3_r;
   
   always @ (posedge CLK)
      if (count == 13'h0) begin
         if (!AN0) begin
            AN0_r <= 1'b1;
            LED <= 7'b0010010; // A
            AN1_r <= 1'b0;
         end
         else if (!AN1) begin
            AN1_r <= 1'b1;
            LED <= 7'b0110001; // C
            AN2_r <= 1'b0;
         end
         else if (!AN2) begin
            AN2_r <= 1'b1;
            LED <= 7'b0011000; // P
            AN3_r <= 1'b0;
         end
         else if (!AN3) begin
            AN3_r <= 1'b1;
            LED <= 7'b0110000; // E
            AN0_r <= 0;
         end
         count <= count + 13'b1;
         if (count > 13'h1000) begin
            count <= 13'h0;
         end            
      end // if (count == 13'h0)
endmodule

This will not give you any compiling errors!

Added after 13 minutes:

I got it what you are trying to do!
Here is the correct version of code!!!

Code:

module pace(   CLK,
               AN0,
               AN1,
               AN2,
               AN3,
               LED
               );
   output AN0,AN1,AN2,AN3;
   input CLK;
   output [6:0] LED;
   reg [6:0]   LED;
   
   reg [12:0]  count;
   reg         AN0, AN1, AN2, AN3;

   always @ (posedge CLK) begin
      if (count == 13'h0) begin
         if (!AN0) begin
            AN0 <= 1'b1;
            LED <= 7'b0010010; // A
            AN1 <= 1'b0;
         end
         else if (!AN1) begin
            AN1 <= 1'b1;
            LED <= 7'b0110001; // C
            AN2 <= 1'b0;
         end
         else if (!AN2) begin
            AN2 <= 1'b1;
            LED <= 7'b0011000; // P
            AN3 <= 1'b0;
         end
         else if (!AN3) begin
            AN3 <= 1'b1;
            LED <= 7'b0110000; // E
            AN0 <= 0;
         end
      end // if (count == 13'h0)
      count <= count + 1'b1;
      if (count > 13'h1000) begin
         count <= 13'h0;
      end
   end // always @ (posedge CLK)
endmodule

kaiser · Jul 14, 2005

Re: convert from VHDL

The goal of this sorce code is to write "PACE" on the seven-segment LED display on the Spartan3 board (starter kit from Xilinx)
Since seven-segment LED displays are timed multiplexed, I will need "something" to tell me to write the first character, then something which tells to write the second and so on. This will be given by a clock.
For the clock signal I use the 50Mhz clock provided on the board. Unfortunately this is too quick to switch beteen digits on the led panel. So I will be using a counter named CTR, each time the counter reaches 2^13 I change the digit to be displayed, an I reset the counter.

But it wont work......when I download the bit file on the board my 4 digits dont diplay the correct information (PACE)
I'm using ISE Webpack provided form Xilinx.
If you gott any code that will do that ....please show me!!(with few explains)

THX

this is the warning i get..:
WARNING:Xst:1710 - FF/Latch <LED_6> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN0_r> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN1_r> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_0> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_1> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_2> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_3> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_4> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <LED_5> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <count_0> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN2_r> (without init value) is constant in block <pace>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN3_r> (without init value) is constant in block <pace>.
WARNING:Xst:1291 - FF/Latch <count_1> is unconnected in block <pace>.

nand_gates · Jul 14, 2005

Re: convert from VHDL

Check out with this code, This should work!
This is written in old days PLD style!

Code:

module pace(   CLK,
               RST_n,
               AN0,
               AN1,
               AN2,
               AN3,
               LED
               );
   output AN0,AN1,AN2,AN3;
   input CLK;
   input RST_n;
   
   output [6:0] LED;
   reg [6:0]   LED;
   
   reg [12:0]  count;
   reg         AN0, AN1, AN2, AN3;

   always @ (posedge CLK or negedge RST_n) begin
      if (!RST_n) begin
         AN0 <= 1'b0;
         AN1 <= 1'b0;
         AN2 <= 1'b0;
         AN3 <= 1'b0;
         count <= 0;
      end else begin
         count <= count + 1'b1;
         if (&count) begin
            AN0 <= ~|{AN0, AN1, AN2};
            AN1 <= AN0;
            AN2 <= AN1;
            AN3 <= AN2;
         end // if (count == 13'h0)
      end // else: !if(!RST_n)
   end // always @ (posedge CLK or negedge RST_n)
   always @(/*AS*/AN0 or AN1 or AN2 or AN3) begin
     LED = 7'b0000000;
     case (1'b1) //synopsys parallel_case
       AN0 : LED = 7'b0010010; // A
       AN1 : LED = 7'b0110001; // C
       AN2 : LED = 7'b0011000; // P
       AN3 : LED = 7'b0110000; // E
     endcase // case(1'b1)
   end
endmodule // pace

maxer · Sep 19, 2005

Re: convert from VHDL

use x-hdl

really useful

maxer

echo47 · Sep 19, 2005

Re: convert from VHDL

Here's another approach. I normally use register initial values instead of a reset input.

Code:

module top (sys_clk, LED_Digit, LED_Segment);
   input                sys_clk;
   reg           [11:0] count=0;
   output reg     [3:0] LED_Digit=0;
   output reg     [7:0] LED_Segment;

   always @ (posedge sys_clk) begin
     count <= count + 1;
     if (count == 0) begin
       if (!LED_Digit[2])
         {LED_Digit,LED_Segment} <= {4'b0111,~8'b11001110}; // P
       else if (!LED_Digit[1])
         {LED_Digit,LED_Segment} <= {4'b1011,~8'b11101110}; // A
       else if (!LED_Digit[0])
         {LED_Digit,LED_Segment} <= {4'b1101,~8'b10011100}; // C
       else if (!LED_Digit[3])
         {LED_Digit,LED_Segment} <= {4'b1110,~8'b10011110}; // E
     end
   end
endmodule

My custom UCF file:

Code:

NET sys_clk PERIOD = 50 MHz;
NET sys_clk        LOC=T9;
NET LED_Digit<3>   LOC=e13;    # left
NET LED_Digit<2>   LOC=f14;
NET LED_Digit<1>   LOC=g14;
NET LED_Digit<0>   LOC=d14;    # right

NET LED_Segment<7> LOC=e14;    #   --7--
NET LED_Segment<6> LOC=g13;    #  |     |
NET LED_Segment<5> LOC=n15;    #  2     6
NET LED_Segment<4> LOC=p15;    #  |     |
NET LED_Segment<3> LOC=r16;    #   --1--
NET LED_Segment<2> LOC=f13;    #  |     |
NET LED_Segment<1> LOC=n16;    #  3     5
NET LED_Segment<0> LOC=p16;    #  |     |
                               #   --4--  (0)

ISE will emit some synthesis warnings about constant values, because some of the output signals never change. That's usually a suspicious situation, but it's ok here.

tkbits · Sep 19, 2005

Re: convert from VHDL

Code:

         if (count > 13'h1000) begin 
            count <= 13'h0; 
         end

Not being a Verilog expert, I want to know if this hex notation means 13 bits or 13 hex digts. If hex digits, then your condition is equivalent to (count > 0).

echo47 · Sep 20, 2005

convert from VHDL

13 is the number of bits, and 'h1000 is the hex value. So 13'h1000 is 1000000000000, and 13'h0 is 0000000000000.
Register count has 13 bits too, so the "if" statement is ok.

The example using that statement has two simultaneous and different assigments to count. That may work (Verilog executes non-blocking statements from top down), but for the sake of clarity I'd avoid doing it.

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Help me convert VHDL code to Verilog

kaiser

Newbie level 5

dBUGGER

Advanced Member level 4

nand_gates

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kaiser

Newbie level 5

nand_gates

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maxer

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echo47

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tkbits

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echo47

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