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Thanks a lot for the reply. I had a feeling PLI is the way, was wondering if Verilog could do it. Is it possible to do using SystemVerilog ? I would be more interested to do it using SV if its possible.
Hi All,
I am trying to perform gate level fault simulation using verilog by simulating faults at the output of internal gates randomly. Say for example, outputs of gate A & B go to inputs of gate C. Now I want to simulate a fault in C by inverting the output of C for 1 simulation cycle and...
Has anybody tried the create_partition command of the IC compiler. I am looking forward to using it and it would be great if someone could help me answer few of the questions that I have.
TIA.
encounter violation
Hi All,
I am using soc encounter for place and route. After nanoroute, when I added fillers and did a 'verify geometry' I got the following warning and hence 1 violation.
Pin of Cell KFILLER_195 at (130.000, 32.920), (132.000, 33.480) on Layer M1 is not connected to any...
set_fix_multiple_port_nets dont touch
can you tell me what meaning does the warning carry ??
and what is its cause ?
I have a verilog code that works fine in modelsim, but once i get the post-synthesis netlist, it doesnt work anymore in modelsim. can this be the cause of this problem ...
Re: parasitic file
Hi,
Can it be generated using primetime using the commands:
write_parasitics -format SPEF filename.spef ? such that it writes all parasitics
annotated on the current design to the file specified
in the filename argument.
Thanks & regards,
Jugantor
vcd dump
can anyone plz tell me how can we generate a .vcd file from a verilog file.
also , how to generate a .fsdb file from the .vcd file?
Thanks & regards,
Jugantor
Re: synopsys question
@diemillio
Thats what I need to know. How can I link those .bsv files (like Edge_FIFO , Socket_FIFO)with the actual DMA file during sythesization ,so that those files are also taken into account(which is not happening now) ?
Its because design_vision doesnt take .bsv...
Re: synopsys question
HI shiv_emf,
you are correct. while using design_vision/DC, I dont need to use -hdl_compiler
. But I am using primepower actually for my power analyis. (the newest version)There I need to use -hdl_compiler .
Its bcoz if I dont use it, then the read_verilog filename.v...
sbpf parasitics
After calculating the power of different instances of a design...i have got the report in terms of the cells....( using "report_power -cell " ) .
my problem is how can i map these cell-power informations into the design file (which is in verilog) ? like...a particular cell-power...
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