how to use set_fix_multiple_port_nets?

[iamczx]

set_fix_multiple_port_nets

first I read in the design and link，then I set the current_design top(top is the top level design).
.....
curret_design top
foreach_in_collection design [ get_designs "*" ] {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
}
compile
wrtie -f verilog -o ./verilog/top.vo -hier $current_design

and the following waring come out:
Warning: Net(s) of type 'tri' are written out. (VO-3)
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
Warning: Changed wire name io to io_wire in module top. (VO-2)
1

It seems the "set_fix_multiple_port_nets" command don't effact at all.
What's the possible cause?
Thanks in advance

 

[rogger123]

warning vo-4

Hi,
you have to make sure you do not have any "don't touch" attribute on any of the ports. If you have any don't touch attributes then DC/PC will not add buffers and will write out assign statments in the netlist.

make sure you check your netlist and see for which port the assign statment is written out. then check if you have a don;t touch on that port.
"most likely clocks"

thakns
rogger

 

[spauls]

set_fix_multiple_port_nets

use this "set_fix_multiple_port_nets -all -buffer_constants -feedthroughs"
instead of what you are using.

 

[iamczx]

assign set_fix_multiple_port_nets

hi spauls, in dc man page,it says:

-all Inserts the same as -feedthroughs
-outputs -constants. Note that logic
constants are duplicated, not buffered.
To buffer logic constants, use the
-buffer_constants option with the -all
option.

So I think -all -buffer_constants is enouth.

And now, I have a new question:
a signal :
wire [7:0] a;
in the design,the bit of a is always:
a[0] = a[4]
a[1] = a[5]
a[2] = a[6]
a[3] = a[7]
so the DC will write assign.

 

[Jugantor]

set_fix_multiple_port_nets dont touch

can you tell me what meaning does the warning carry ??
and what is its cause ?

I have a verilog code that works fine in modelsim, but once i get the post-synthesis netlist, it doesnt work anymore in modelsim. can this be the cause of this problem ?

Thanks.
--Jug

 

[iinetd]

Hi,
Pls add
change_name -h -rule verilog
before dump your netlist.