Gate Level Fault simulation using verilog

[Jugantor]

Hi All,

I am trying to perform gate level fault simulation using verilog by simulating faults at the output of internal gates randomly. Say for example, outputs of gate A & B go to inputs of gate C. Now I want to simulate a fault in C by inverting the output of C for 1 simulation cycle and reverting it back in the next. This can be done using the force and release commands.

My question is how do I automate this step ? like how do I randomly select the outputs of my gates of the DUT from my testbench, without explicitly having to mention what gate to select ?

Right now, as you can see in the code below, I am explicitly saying which gate to select based on the value of sel. This step gets cumbersome when the number of gates is huge (in this case 35)

sel = {$random} % 35;
if (sel == 6'd0)
        begin 
		#1 force a0.n12 = !a0.n12;
		#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
		#1 release a0.n12;
  	end   	
	
	else if (sel == 6'd1 )
	begin
		//node2
		#1 force a0.n14 = !a0.n14;
		#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
		#1 release a0.n14;
  	end

	else if (sel == 6'd2)
	begin	
		//node3
		#1 force a0.n15 = !a0.n15;
		#1 $fdisplay (desc3, "Error at gate #%d | %d | %b",sel, col_in, xtraOut, cout, z1[3], z1[2], z1[1], z1[0], z2[3], z2[2], z2[1], z2[0]);
		#1 release a0.n15;
  	end

Any kind of help is highly appreciated.

Thanks!

 

[jbeniston]

Not sure how you can do it in pure Verilog. You could probably do it more easily via the PLI, as you can walk through the gates in the design dynamically.

 

[Jugantor]

Thanks a lot for the reply. I had a feeling PLI is the way, was wondering if Verilog could do it. Is it possible to do using SystemVerilog ? I would be more interested to do it using SV if its possible.

 

[santhosh007]

i have done some time back same thing. i have return small python script to take care of the force and release statements.
i just give the one text file which has the node and the value that needs to be forced. script lanuches any number parallel jobs and as soon as one job is completed, it will force the node in the text file. the testbeach can be either in verilog or specman or e ..