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This is my academic project.Here I haven't designed any clock source.And I will be giving clock from the test bench only.In that case what I can do.Can I specify uncertainty as some percentage of clock frequency that am using?
During synthesis I have defined clock as 100Mhz. Now what is the criteria to set the clock latency,slew and latency.
In my project i havn't designed the clock source I am assuming there is an external source suplying the clock.In that case what values I have to use?
Sir am new to this tool.In the .lef file 'tsmc18_6lm.lef' only 2 pads of class power
1.MACRO PVDD1DGZ
CLASS PAD POWER ; and
2. MACRO PVSS1DGZ
CLASS PAD POWER ;
these 2 I have used as core power pads now which pads I can use a IO power pads can I use the same pads?
Sir,
am using TSMC library in that I have used PVDD1DGZ and PVSS1DGZ as core power pads.
Now which pad I have to use as the IO power pads.I couldn't find any other pads with name VDD or VSS in it.
Sir,
I didn't understand what u said.I used this library in RTL compiler now I want to export it to cadence encounter and I don't have any LEF file which have information of this memory instance.
* CONFIDENTIAL AND PROPRIETARY SOFTWARE/DATA OF ARTISAN COMPONENTS, INC.
*
*...
sir,
I have some libraries for memory like ram_256x16A_typical_syn.lib and but I don't have .LEF files for this modules can I generate LEF files for this libraries ?
sir,
to do the DRC check I have added technology mapping file and rule files but they are asking for some rule set I have attached a screenshot what I have to do ??
Sir this is part of my M-tech project in stereo vision
I have 2 images from camera(am taking stereo images from vision.middlebury.edu/stereo/) and my processing is done on this images in this case if i am designing an ASIC for the same should I include the memory for storing this image in my IC...
Sir if I code in conventional style won't it be getting synthesized to flip flop based memory. For which the area requirement will be almost ten times than that of 6T sram cells. Then how efficient will be my design ??
Actually in my project we have made modification to an existing algorithm...
Sir,
am doing project in Image processing while doing its FPGA implementation I used the block ram resources.Now for designing ASIC in cadence encounter for the same what memory I have to use.I don't know whether IP cores are available or not in our system.How can I find whether IP cores are...
Sir,
I have generated netlist for a 16 bit counter using Encounter RTL compiler.In the synthesis I set the clock as
define_clock -period 3500 -name clk [find / -port clk] and in the timing report generated a have a positive slack
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -...
Sir ,
I used Cadence RTL compiler to generate the netlist.Then tried to do netlist simulation in NCLAUNCH
files used netlist.v (netlist generated by rc) and test bench
When I compiled there was no error but upon elaborating test bench am getting this error
but am getting this error...
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