On what basis we will set the clock unsertinity,slew and latency?

[JineshKB]

During synthesis I have defined clock as 100Mhz. Now what is the criteria to set the clock latency,slew and latency.
In my project i havn't designed the clock source I am assuming there is an external source suplying the clock.In that case what values I have to use?

 

[ads-ee]

Not sure about the latency and skew as that is more or less a function of your system timing budgets, but you should add the uncertainty as that will encompass the total cycle-to-cycle jitter of your clock source, which will affect the synthesis timing budget of your register to register timing. The amount of uncertainty you'll had will have to come from the clock source jitter specification.

 

[JineshKB]

This is my academic project.Here I haven't designed any clock source.And I will be giving clock from the test bench only.In that case what I can do.Can I specify uncertainty as some percentage of clock frequency that am using?

Not sure about the latency and skew as that is more or less a function of your system timing budgets, but you should add the uncertainty as that will encompass the total cycle-to-cycle jitter of your clock source, which will affect the synthesis timing budget of your register to register timing. The amount of uncertainty you'll had will have to come from the clock source jitter specification.

 

[ads-ee]

If this clock is just a simulation clock in a testbench for a functional simulation (as opposed to a timing simulation) then you can just use an ideal clock unless there is something specific about your design that manages the clock skew, insertion, and/or jitter.

You can always add a 100-200 ps of jitter to emulate the real world, but it's going to take a bit of work to do it randomly. I'd suggest for a functional simulation to use an ideal clock.