JineshKB
Junior Member level 1
Sir,
I have generated netlist for a 16 bit counter using Encounter RTL compiler.In the synthesis I set the clock as
define_clock -period 3500 -name clk [find / -port clk] and in the timing report generated a have a positive slack
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(clock clk) capture 3500 R
-------------------------------------------------------------
Timing slack : 2501ps
Start-point : temp_reg[0]/CK
End-point : temp_reg[15]/SE
but on netlist simulation my output is just uu
sir what could be the possible reason for this (behavioral simulation is working fine)
I have generated netlist for a 16 bit counter using Encounter RTL compiler.In the synthesis I set the clock as
define_clock -period 3500 -name clk [find / -port clk] and in the timing report generated a have a positive slack
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(clock clk) capture 3500 R
-------------------------------------------------------------
Timing slack : 2501ps
Start-point : temp_reg[0]/CK
End-point : temp_reg[15]/SE
but on netlist simulation my output is just uu
sir what could be the possible reason for this (behavioral simulation is working fine)