Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by jerryhuang

  1. J

    lmgrd problem - command " lmgrd -c license.dat"

    lmgrd -2 -p I just install cadence ic5141 on linux redhat 4.6, if I do not run the " lmgrd -c license.dat ", can I still use the cadence for design circuit ? is there any problem? what is the function of the command " lmgrd -c license.dat" for the cadence license.dat?
  2. J

    how can I get a transferfunction about a loop filter in pll

    can some guy give me some reference or just a simple math way to this problem ,many thanks
  3. J

    what's the meaning of the fourth-order type2 charge pump pll

    thanks,does the fourth-order pll have good noise performance than third-order pll?And I still don't know the meaning of typeII or type I ?for a cppl,how can I modle the open-loop response ,does the type also depend on the loop filter transfer function?
  4. J

    what's the meaning of the fourth-order type2 charge pump pll

    thanks
  5. J

    Problem with charge pump PLL

    is that spur of pll it is a fractional pll ,so i think it is fractinal spur
  6. J

    Problem with charge pump PLL

    is that spur of pll my locking frequence is 2Ghz,VCO frequency variation limits is what? reference frequence is 20Mhz,so it is not the reference spur and its' hamonics,I think it is fractional spur?
  7. J

    Questions about pll jitter

    2 amarnath the pfd works at 20Mhz,why the ripple frequence is 120Khz?
  8. J

    Questions about pll jitter

    thanks,amarnath,my pll is a charge pump kind pll,my problem is when my pll is locked,see from the control votage of vco ,you will see a large and low frequence (about 120khz) ripple,and the votage ripple got a ampiltude as large as 2mv,so the output frequnce of vco has a large derivation as...
  9. J

    Problem with charge pump PLL

    is that spur of pll my pll is a charge pump kind pll,my problem is when my pll is locked,see from the control votage of vco ,you will see a large and low frequence (about 120khz) ripple,and the votage ripple got a ampiltude as large as 2mv,so the output frequnce of vco has a large derivation as...
  10. J

    Questions about pll jitter

    hi,amarnath , pfd is mainly couse of what spe of pll?I also have a large ripple when my pll is locked,and the ripple is not decresed whit time pass,what is main reason of this jitter?should I use a low pass filter to decrese this ripple,the ripple got a timepieriod of 2us see foem the control...
  11. J

    What is the relation between the dead zone of phase detector and the jitter ?

    what is the relation between the dead zone of phase detector and the jitter , spur ,bandwith of the pll? thx!
  12. J

    how to bulid a acumulator in matlab simulink

    can you give me a s-function sample about accumulator,and how to determin the bits of the accumulator
  13. J

    how to implement reset circiut for pll

    what 's the name of this kind of circuit?
  14. J

    Regarding Sigma Delta Modulator

    arp, i met the same problem with you ,how to implement the digital logic of sigma delta in the simulink ?for example ,the quantizer,the acumulator,the unit delay......can someone give me a sample ,thanks
  15. J

    some question about Delta-sigma ADC

    do you have email,shall we have a chat on the topic,thanks,are u from uestc?hehe
See more

Part and Inventory Search

Back
Top