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Recent content by guguwuwu

  1. G

    who can explain this DSM matlab code to me - I am new for this

    I don't know your real means and think of for: "tone_bin" is a variable to determine the length of the signal. "u = 1*(nLev-1)*sin(2*pi*tone_bin/Nfft*t)" is an sine signal. The frequency is tone_bin/Nfft.The amplitude is (nLev-1). "spec = fft(v.*ds_hann(Nfft))/(Nfft*(nLev-1)/4);" is an FFT...
  2. G

    verilog language synthax

    Generally,the number we get from ADC is an integer.I suggest that you change your signal into a complement of integer. You can multiply the signal by 2^n and then change them into complement of integer(in Matlab). At last, you just need shift the result right by n bits. ---------- Post added...
  3. G

    Help in Verilog Code for FIR Filter

    I'm sorry I don't know how to express a fractional number in verilog. But when I design a sensor detection circuit, the numbers from ADC are integer. I will make filter coefficients multiplied by 2^n and change them into binary integers in Matlab. And finally I just need shift the result right...
  4. G

    Verilog synthesis error

    It's difficult to identify the specific problems without codes.But you can look at the following URL first, and maybe it's usefull. https://www.edaboard.com/threads/240303/
  5. G

    why doesn't this circuit oscillate

    You should confirm the following: (1) (It is an amplifier or an OP amplifier). (2) The amplifier gain in the oscillation point is large enough too. (3) The phase shift of the amplifier is 180 degreee too in the oscillation point. You can make the bandwith and gain of amplifier a vety large...
  6. G

    verilog signed type conversion

    It's very easy for verilog. module abs_test(da_in,da_out); input[8:0] da_in; output[8:0] da_out; assign da_out=(da_in[8])? (0-da_in):da_in; endmodule
  7. G

    how pcie works in fpga

    Maybe you can use an interface-chip between the PC and FPGA, such as MAX232, CP2102. It's very easy.And then you just need to know the time sequence from the datasheet.
  8. G

    Quartus || - Timing simulation problem

    Maybe you should join a global clock to the code. If it is necessary, you can change your code into synchronous logic. ---------- Post added at 08:43 ---------- Previous post was at 08:41 ---------- It's difficlut to identify specific problem without any codes.
  9. G

    Help in Verilog Code for FIR Filter

    Yes,you can write direct statements for addition & multiplication in the code like that. But you should change the data into its complement.
  10. G

    Why Asynchronous Reset in our Design ?

    If we adopt an asynchronous reset, it can take effect immediately. But I do't think we have to use the asynchronous Reset。 Refer to the following website： http://forums.xilinx.com/t5/PLD-Blog/That-Dangerous-Asynchronous-Reset/ba-p/12856 ---------- Post added at 13:36 ---------- Previous...
  11. G

    Initializing memory array in Verilog with test data from file

    Write the data into a file,such as .hex, .mic. example: `ifdef NO_PLI altsyncram_component.init_file = "fir_zero.rif" `else altsyncram_component.init_file = "fir_zero.hex" `endif ,
  12. G

    How to find gate counts?

    there is the simulation reslut.
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