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Recent content by graphene

  1. graphene

    Connecting modules in VHDL

    sorry misunderstood sub programs for sub modules.... anyways wasted/spent time to learn this.. will do as you suggested thank you both @ads-ee and @FvM
  2. graphene

    Connecting modules in VHDL

    @ads-ee thank you. it works. however, can these sub modules be included in packages and the package (for ex. 'work.my_pkg.all') be called instead? ----------- the reason why I am asking this is, in some cases I may have a project in C: drive and other project in D: drive or may be in the shared...
  3. graphene

    VHDL twos complement to decimal conversion

    @ads-ee: wonderful... never though about it... thank you a lot mate.
  4. graphene

    Connecting modules in VHDL

    I created 3 modules namely PGA, ADC, DAC in 3 different folders and simulated and verified them successfully. Each of the three has 4 or 5 other sub-modules.. I now need to create a TOP module that connects to all the 3 modules and also their respective submodules, in this case the name of...
  5. graphene

    VHDL twos complement to decimal conversion

    @kommu4946 .... thank you once again... @ads-ee... thank you .I understood my issue in adding to sensitivity list... @axcdd... using abs also works... thank you.. - - - Updated - - - @ads-ee Can you please tell me what this OFFSET_BINARY to be given to the DAC. I did not understand the...
  6. graphene

    VHDL twos complement to decimal conversion

    in my first post where i had asked for a decimal conversion was wrong... i need a two's complement to binary conversion... in real, my adc gives twos complement output which is input to my fpga and the fpga should be programmed to provide binary output to the dac. this is where I am struggling
  7. graphene

    VHDL twos complement to decimal conversion

    thank you kommu4946... but this is what I compiled and I get wrong outputs. seems problem with my code.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity adc_binary_converter is port( IN_TWOS_COMPLE : in signed (7 downto 0); OUT_BINARY : out...
  8. graphene

    VHDL twos complement to decimal conversion

    Sorry, I was meaning to convert that into a BINARY form instead of decimal form. I want to know how to convert a TWO's complement into a binary form to feed to the DAC --------------- Mathematically>>>>. check for the MSB for a ZERO or ONE to know if it is positive (MSB of 0) or negative (MSB...
  9. graphene

    VHDL twos complement to decimal conversion

    I want to convert the the output I get in TWO's complement form from a ADC to decimal form before I feed it into a DAC. I am know to do that matmatically but I am unbale to frame a logic in VHDL. Can someone help me with suggestions? Is there any suggestions for such conversion functions or...
  10. graphene

    FPGA-final implementation XIlinx ISE

    I am using Xilinx ISE. I have completed P&R and also generated '.bit' files. I created PROM file with impact.I am able to see the PROM associated with my bitsream file. I saved the file and closed impact. I also have my Platform-II USB cable connected to my borad with FPGA device in it, powered...
  11. graphene

    [SOLVED] Spartan-3 External pinning on the FPGA

    @pbernardi I checkd the package it was not the wrong one. I found the answer myself. With the mouse pointers on the banks, the names of the pins in the bank lets say IO_L21N_2 can be found and that corresponds to the pin numbers. I sincerely thank you for your reply. I also got to know some...
  12. graphene

    [SOLVED] Spartan-3 External pinning on the FPGA

    I now want to place the input/output signals perfectly into a particular pin as described in my circuit plan. I am using Spartan-3 XC3S400, XIlinx ISE 14.7. As shown in figures below, I need the pin 67, 65, 64 to be assigned for particular scalar ports. However, when I use my Planahead 14.7...
  13. graphene

    FSM design using 3 process

    Thank you friend... I dint not understand about the RESET in the transition. Can you please explain me once again. 1) The remaining I have corrected.Pleas let me know that. Thanks in advance. 2) Also another basic question. Can a state diagram have multiple inputs from nowhere ?? I guess the...
  14. graphene

    FSM design using 3 process

    Hi, I am designing an FSM for my project. I am from SW background but new to VHDL and Xilinx. 1) I have a counter with just CLOCK, and RESET inputs and a OUTPUT 2) I have a PISO with RESET, CLOCK, PARALLEL DATA and LOAD inputs and SERIAL OUTPUT. I now need to create an FSM that controls how...
  15. graphene

    How can i extract .LIB file from encounter?

    I think you cannot directly extract a .lib file from encouter (it may be encrypted or restricted for aceess) but probably a LEF file can be extracted.
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