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Re: tiny verilog question:)
verilog is not interpreter based, it is compiled - I think this is a wrong statement - u should send a mail to the author and ask him directly what he meant -
ag
for ultimate chip simulations ultimately you have to have the model in HDL - this is how it is done in industry - however for co-simualtions the HDL models is replaced with spice netlist
ag
Re: book on RTOS
i have searched for such a book a lot but doesn't seem one is available online ...but there are many class lecture notes available from many US universitites - also check for notes in www.uclinux.com
ag
from u r mail i think u want solutions for AVR line - u can check out the site www.avrfreaks.com - this site is offcialy maintained by the AVR group and has huge info including prices
ag
Hi,
this book is online - **broken link removed** - it gives a holistic view and is quiet good - then u need to decide which part you want to work on - if you want to work in backend you can try a GNU tool Archimedes or Microwind's student edition - both available for free -
ag
Re: RF!!! i am puzzled!!!
Hi,
This is a structured approach - the first thing is to be very conversant in linear integrated circuit design - then you move to non-linear circuit design - understandbly your problem is that you are doing a lot of dog work - but the fact that you are putting things...
Re: final year project
Since your background is electronics and communication - a good project is in radio frequency CMOS analog integrated circuit design - if you look at what companies want you will find the demand and pay for RFIC designers are much higher than digital designers or software...
hi,
simple way to describe this is as follows -
in digital verification you only probe some singnals at particular times which means that you go unaware about what happens to other signals at other times -assertion means 'to assert' - it is a way of writing expressions on a signal or group of...
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