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Recent content by gck

  1. gck

    Power gating in synopsys

    Hey You need to create a UPF file as an input to dc_shell. UPF file contains the details of power domain, and here you can use "create_power_switch" command to do that. You also need to add isolation cells. Just man these commands for further information,
  2. gck

    Dynamic Power Analysis

    Hey, I have design written in VAMS. I need to see its power trace. I have Cadence tool set install. I could manage to get VCD file. I read on some online post that I need TCF and SAIF files too. I got how to do it, but not successful. My question is, what tool I need now to see power trace...
  3. gck

    Suggestion for Verilog - AMS

    HI, For my a new project, I have been asked to get familiar with Verilog-AMS. I using Verilog from past 4-5 years. But, I am wondering, if any suggestion for how to jump-start Verilog-AMS and any areas which in particular should be looked at. Thanks
  4. gck

    Registering both inputs and outputs

    hi Shaiko, Let's consider that, the IC-A don't have registered output and the other IC-B which taking input from IC-A has registered input. Timing requirement for the output port of IC A will be Tp+Tdelay(combinational inside A)+output Pin delay + track delay between A & b + input pin delay of...
  5. gck

    [SOLVED] lookup table in xlinx using verilog

    hi, Please check the syntax for User Defined Primitives (UDP) Here is some sample code from IEEE Spec of Verilog primitive multiplexer (mux, control, dataA, dataB); output mux; input control, dataA, dataB; table // control dataA dataB mux 0 1 ? : 1 ; // ? = 0 1 x 0 0 ? : 0 ; 1 ? 1 : 1 ; 1 ? 0...
  6. gck

    verilog question: instantiation Always block

    hey Steve, what exactly are you trying to do? question is not clear.
  7. gck

    help:how to solve this xilinx translate trouble

    Hey, can you post code for module "DIV_12x12_FRA". or have you tried to synthesize and translating DIV_12x12_FRA module. I think problem is with this module.
  8. gck

    enter a array with two input clock using verilog

    Hi Igeorge123, Is it that even address of MEM_CH1 are clocked by clk1 and odd address are clocked by clk2. If yes, then why don't you create two banks and make the address decoding mechanism to sort out the different clock triggering problem. Let me know, is this possible or any other...
  9. gck

    Buffers/Inverters in clock path: Delay vs signal strength

    hey Rohit, You are analyzing in right direction, but a few things which are need to be looked with different perspective. Here is a pdf, which has very good analysis of this problem https://courses.ece.ubc.ca/579/clockflop.pdf
  10. gck

    instantiation of EDIF file in ActiveHDL

    hey, Check out this article, MANUAL: Active-HDL 9.1 Software Manual - Using EDIF Netlists with Active-HDL (11/2/2011)
  11. gck

    [SOLVED] Multi-source in Unit bug in Verilog

    hey, for else condition of the SPI_CS in first always block, make pointer = 0. This should work.
  12. gck

    Tri-state buffer high impedence

    Hi, Here is the CMOS level diagram for tristate inverter. Similar approach has been taken for tristate buffer also. For additional information please look in to CMOS VLSI Design by Neil Westy Chapter 1, page no 15
  13. gck

    [SOLVED] Multiply driven in VHDL

    hi iVenky, Multiply Driven is the condition when a single signal is been forced by multiple drivers or multiple inputs. In case of code under consideration, generate will generate 8 statements out of the single statement written under it. Because of which signal "accum" will be driven by a(0)...
  14. gck

    FIFO - CMOS, number of input clock cycles required

    hey ramyyy, which one is the correct frequency for read cycle. You wrote both 500MHz and 300 MHz as read cycle frequency.
  15. gck

    Verification for newbie

    Hi, Here is book, I would like suggest, Writing testbenches: functional verification of HDL models By Janick Bergeron Verification is an art. Thinking process for verification is way different than design. This book has helped me lot for switching between Design to Verification. You atleast...
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