Registering both inputs and outputs

[shaiko]

Hello,

It's good practice to register all input signals to an FPGA and sychronize them to our clock domain...but why should we register the outputs?

Suppose a combinatorial FPGA signal travels to an output port - It's safe to assume that the recieving end of this signal is an IC that also follows the same synchronous design rules and also registers inputs.
So, why should we register outputs?

 

[gck]

hi Shaiko,

Let's consider that, the IC-A don't have registered output and the other IC-B which taking input from IC-A has registered input.
Timing requirement for the output port of IC A will be
Tp+Tdelay(combinational inside A)+output Pin delay + track delay between A & b + input pin delay of B + setup time for FF in B.

Again, Tdelay(combinational inside A) will be different for different output pin of A. Because of this, these path may become critical path for design.
But if you register the output, then it minimizes these effect.