enter a array with two input clock using verilog

[lgeorge123]

I have two input clocks , clk1 and clk2 , two different inputs port of 8 bits , ADC1 and ADC2 and a array of 8 bits with size 8192 , i.e reg [7:0] MEM_CH1[8192] . With positive edge of clk1 ADC1 data is shifted into MEM_CH1[0] , again with clk2 ADC2 data is shifted into MEM_CH1[1] , next positive edge of clk1 ADC1 data is shifted into MEM_CH1[2] , again with clk2 ADC2 data is shifted into MEM_CH1[3] , this keep on until MEM_CH1 array is fulled , how can it be done using verilog ???

 

[gck]

Hi Igeorge123,

Is it that even address of MEM_CH1 are clocked by clk1 and odd address are clocked by clk2. If yes, then why don't you create two banks and make the address decoding mechanism to sort out the different clock triggering problem.
Let me know, is this possible or any other constraints are there for design. So that, further or different suggestion can be worked out.

 

[arunbv123]

integer i,j;

initial
begin
i=0;
j=1;
end

always @ (clk1 or clk2)
begin
if (clk1)
begin
MEM_CH1<=ADC1;
i<=i+2;
end
else
begin
MEM_CH1[j]<=ADC2;
j<=j+2;
end
end

//but this only work if clk1 and clk2 are not synchronous. If they are synchronous then 2 if statement if(clk1) & if (clk2) has to be written and else has to kept blank to be RTL compliant

 

[jimwu88]

This code may work in simulation, but it's not going to map well with actual FPGA hardware.

integer i,j;

initial
begin
i=0;
j=1;
end

always @ (clk1 or clk2)
begin
if (clk1)
begin
MEM_CH1<=ADC1;
i<=i+2;
end
else
begin
MEM_CH1[j]<=ADC2;
j<=j+2;
end
end

//but this only work if clk1 and clk2 are not synchronous. If they are synchronous then 2 if statement if(clk1) & if (clk2) has to be written and else has to kept blank to be RTL compliant

 

[FvM]

This code may work in simulation, but it's not going to map well with actual FPGA hardware.

Yes, obviously. It probably won't work even in simulation, because it's very dubious Verilog syntax. May be you had an edge sensitive condition in mind, but you didn't write it.

I also agree with gck, that there has been no reasonable argument yet, why to store both data streams to one memory array.

Referring to real FPGAs, the problem probably suggests to use a dual port RAM, which is available with most recent FPGA series. This isn't firstly a Verilog problem then, rather than of understanding the hardware requirements. Secondly, dual port RAM can be usually inferred from behavioral Verilog code, the trick is to understand the specific syntax, which may be a bit different between vendor tools. But in my opinion, the problem is beyond basic Verilog programming questions.

It would be helpful to know a more complete problem specification.