[SOLVED] Multi-source in Unit bug in Verilog

[usafape]

I am writing a slave spi controller and I have a counter I want to clear when CS goes high. I am getting a multi-source error. Can someone help me with a better approach? Here is my code`

module spigpio(	SPI_CLK, 
						SPI_CS, 
						SPI_MOSI, 
						SPI_MISO, 
						DEBUG
						);

	parameter ADDRESS_WIDTH = 8;
	parameter DATA_WIDTH = 16;
	
   input SPI_CLK, SPI_CS;
   input SPI_MOSI;
   output SPI_MISO;
    
	output [4:0] DEBUG;

	reg [4:0] pointer = 0;
	reg [DATA_WIDTH-1:0] rs = 0;
	reg rw = 0;

	assign DEBUG[0] = SPI_CLK;
	assign DEBUG[1] = SPI_CS;
	assign DEBUG[2] = SPI_MOSI;
	assign DEBUG[3] = SPI_MISO;
	assign DEBUG[4] = rw;

    
	always@(negedge SPI_CLK) 
	begin
		if (SPI_CS == 1'b0)
		begin 
			rs[DATA_WIDTH-1:1] <= rs[DATA_WIDTH-2:0]; //Shift data to the left
			rs[0] <= SPI_MOSI;	//Save new bit from MOSI
			if (pointer == 0) rw <= rs[0];
			
			pointer = pointer+1;	
		end
	end
	always@(posedge SPI_CS)
		pointer <= 0;
endmodule

Thanks

 

[gck]

hey,

for else condition of the SPI_CS in first always block, make pointer = 0.
This should work.

 

[usafape]

It worked!

Thanks