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Recent content by gautamvsharma

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    PROBLEM WITH EVENT BASED RESET GENERATION SPARTAN-6 using VHDL

    Hello all, I am facing one problem and need urgent solution, please look into code and let me know where is the problem. Problem: when i emulate this code on spartan 6, 1) the logic is accepting user reset, 2) but after event based local reset generation when i switch the reset to global reset...
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    call task from case statement which contains wait statement in verilog?

    Hi All, I am just stumbled with one of the process that i need to execute for my current assignment? I tried above method what is mentioned in question but didn't worked out. Can anyone provide me an easiest way out for following function: I have to write testcases in verilog for my VHDL...
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    Routing resource starvation in spartan-6?

    HINT for you comment: As i told you, You can open NGC and EDIF netlist ans can see complete path(after synthesis, tool will add up best path to meet all constraints & strategies entered. You can see the written NGC and EDIF is similar to ADA language where net to net path is given. there itself...
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    inout port problem vhdl testbench

    Hi TrickyDicky, It seems like metastable to me, because it is not in either state, and the second thing, as if you refer the code, than you can see, i have described the correct driving statement for Z and process generated reset signal mapped to "tb_tst_out". I resolved the issue temporary...
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    inout port problem vhdl testbench

    Hi All, i have a problem, while i am driving my INOUT pin named "reset" of testbench(vhdl) connected with my TOP LEVEL(vhdl) which has one module generating clock and reset for all fpga modules and I/Os. The problem is while i am trying to drive the pin by generated local...
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    Routing resource starvation in spartan-6?

    u can modify the netlist(NGC or EDN)by only doing it manually, there is not tool which does user specific optimized routing as per design goal automatically. because auto routing is specific to design synthesis yield of target device with respect to its manufacturer, you can use the auto routing...
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    Can Someone Provide me with some documentation on SerDes Verification

    You can find it in mentor.com in search write serdes verification
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    Routing resource starvation in spartan-6?

    still u can modify ur netlist(NGC or EDN), by manual selection of route path and try to synthesize it, is this bouncing effects to the timing requirements of your design?? Regards,
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    I want to learn VLSI, FPGA and ASIC

    What do you mean by above..? Are u looking for HDL entry? or synthesis? or simulation?... Your question has no direction...........so give us the way to serve your need.....
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    Help me, How to evaluate the performance of the Sigma-delta ADC in Simulink.

    correct...
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    Help me, How to evaluate the performance of the Sigma-delta ADC in Simulink.

    Hi Friend, I worked on 24-bit Sigma delta ADC architecture of TI based ADC. as per your problem, you must have 2^(resolution of bit) bins and then try to plot histogram in matlab and try to write macro in MATLAB for OE and GE measurement. then you can conclude your decimation filter is doing...
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    Advanced Digital Design Books with verilog HDL

    sameer palnitker is good
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    Settinng environment using modelsim for systemverilog

    Thanks vlsi_whiz and sam33r, both suggestions were stand valuable for me, I have RTL written on VHDL, which is synthesizable. I need to do randomize coverage driven verification in SV, I am using MODELSIM 6.4.. please let me know, if i am wrong in some steps, first, I will creat, verilog...
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    System level design and simulation

    for communication system simulation, simulink is the very best tool to utilize.
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    Settinng environment using modelsim for systemverilog

    Thanks dear for your response, can you please tell me, how do i create .SV for my VHLD/VERILOG design file, and how do i simulate it in modelsim environment.? Thanks in advance.
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