Settinng environment using modelsim for systemverilog

[gautamvsharma]

Hi,

I have some problem that i need to share and expecting some master reply to solve my problem,

I have RTL design written in VHDL, i did functional simulation using VHDL & Verilog testbence, as verilog have more & effective simulation constructs.

Now i need to write testcases using SYstem verilog, and i need to build environment using modelsim v6.4.

So anyone can help me to build environment for RTL verification with Systemverilog & Modelsim?

Any detailed help is highly appreciated.......

Thanks in advance...

 

[ljxpjpjljx]

for modelsim you only add "-sv" option ,then you can do simulation for SV!

 

[gautamvsharma]

Thanks dear for your response,

can you please tell me, how do i create .SV for my VHLD/VERILOG design file, and how do i simulate it in modelsim environment.?

Thanks in advance.

 

[vlsi_whiz]

Hi,

First, you create a Verilog wrapper for your blocks/ top-level block that you want to verify. Then you instantiate this wrapper in the SV testbench file and proceed by adding test cases etc..
you must compile the VHDL RTL first, then the verilog files followed by the SV files and then simulate the top-level testbench passing the testname in the vsim command like:

vsim +incdir +.... -f <file_name with compile list> -sv +TESTNAME = <test name> ...etc

 

[sam33r]

1) add modelsim // add the appropriate version
2) setenv MODELSIM modelsim.ini// modelsim.ini contains all the initial settings and must be in the directory
3) vlog *.vp // compiles all verilog files
4) vlog -sv -mfcu *.sv // compiles all systems verilog files

 

[gautamvsharma]

Thanks vlsi_whiz and sam33r, both suggestions were stand valuable for me,

I have RTL written on VHDL, which is synthesizable.
I need to do randomize coverage driven verification in SV, I am using MODELSIM 6.4..

please let me know, if i am wrong in some steps,

first, I will creat, verilog wrapper instantiation model, then create new .sv file using Modelsim.
secondly, I will instantiate newly generated wrapper with .SV Testbench file(re-instantiation of core RTL via verilog wrapper model)
thirdly, I will write different testcases in it..

If i am correct by above steps, I can simulate my design functionally, and can see the waveforms.

Is there any environment variable or any background switch is required to use all component of systemverilog in modelsim?

Thanks,
Gautam

 

[ljxpjpjljx]

if you only need system verilog code to write test case , you can add "sv" option when run simulation!