PROBLEM WITH EVENT BASED RESET GENERATION SPARTAN-6 using VHDL

[gautamvsharma]

Hello all,

I am facing one problem and need urgent solution, please look into code and let me know where is the problem.

Problem: when i emulate this code on spartan 6, 1) the logic is accepting user reset, 2) but after event based local reset generation when i switch the reset to global reset path it is generating one more reset of variable time(<100ns, pls consider board clock 15ns). this is not expected. and processor is getting reset one more time.

Please look into code and suggest if there is some problem(I have already simulated the code and working as per requirement)

Start: Code starts here
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sig1_gen: process (fidoclk_buf_s) is
begin
if Rising_edge (fidoclk_buf_s) then
sbabot_reg_s <= sbabot_reg_s(14 downto 0) & sbabot_p; --sbabot is the main event signal
end if;
end process;

sig_gen: process (fidoclk_buf_s,sbabot_p) is
begin
if(sbabot_p = '0')then
cmd_ns <= '1';
cmd_rst_count_s <= 0;
cmdrst_lock_s <= '0';
cmdcnt_en_s <= '0';
sbabotlh_reg_s <= (others => '0');

elsif Rising_edge (fidoclk_buf_s) then

if(sbabot_reg_s(1) = '1' and sbabot_reg_s(3) = '0')then
cmdcnt_en_s <= '1';
end if;

if(cmdcnt_en_s = '1')then
if(cmd_rst_count_s = 13335)then --local reset of 200us(13335*15ns)
cmd_ns <= '1';
cmd_rst_count_s <= 0;
cmdcnt_en_s <= '0';
else
cmd_rst_count_s <= cmd_rst_count_s + 1;
cmd_ns <= '0';
end if;
else
cmd_ns <= '1';
cmd_rst_count_s <= 0;

end if;
end if;
end process;
rst_sel_s <= '1' when sbabot_reg_s(6) = '1' else '0';
locrst_ns <= cmd_ns when rst_sel_s = '1' else fido_rst_s;
mrst_np <= locrst_ns; --ultimate reset going out to fpga modules
fido_rst_out_p <= locrst_ns; --ultimate reset going out to processor
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End : Code Ends here


Please let me know your comments, whether it is a GSR problem which is not giving me access for sometime to assign global reset path?

Your answers will be highly appreciated.

--
Gautam