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Recent content by Gagan_SJSU

  1. G

    common emitter configuration of BJT

    What is the small signal gain? What is the input resistance (r pi), assume beta = 100? How much higher can the current go before the transistor saturates? I have attached the circuit..please tell me how to solve such a circuit..what formulas are to be used
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    op amp and iits unity gain

    Hi friends I have a question to ask....if my op amp has a DC gain of 10000 and one pole at 1khz...what would be my frequency where the gain would cross unity..,also please explain me the method .. thanks Sunny
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    scope probe impedance for spectrum analyzer

    Thanks Dave and Pico..thanks a lot for your help
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    scope probe impedance for spectrum analyzer

    Hi Friends I was wondering what is the meaning of scope probe impedance of a spectrum analyzer and what is its typical value? And what is the difference between setting this impedance to 50 ohms as compared to when it is lets say 1Mohms? please let me know Thank you Sunny
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    Phase error minimization

    Hi All I have designed a PLL at 60Hz to lock onto AC mains for a solar inverter. I am using a first order filter and I am not able to achieve the phase margin. I have used a higher order filter but things do not work. What else can I do to improve my phase. I can only afford 2degree phase error...
  6. G

    cutoff frequency of seond order low pass filter

    How do we choose teh natural frequency of a closed loop??
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    How to improve phase error

    hi all In a PLL LPF filter, I am not able to achieve the required phase margin. I am using a second order passive filter. How can I improve my phase error. I can afford a max of 2 degrees but it is more than 30 degrees phase error? Please reply
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    Relation between lock range, cutoff frequency and phaseerror

    hi all I am working on a PLL. The maximum phase error that I can afford between my input and output is 2 degrees. The PLL lock range is 47Hz to 63Hz with a reference of 60Hz grid 3v peak to peak. VCO center frequency is 55Hz ...I am having too much phase lag...what is needed to reduce it....I am...
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    How to design a PLL locked at 60 Hz

    Thank you Friends The things that both of you said are totally right. This PLL will be implemented using a code later on. Can you suggest me a way to start designing the filter because I believe I have to use control theory in it so where should I start from. I have to decide upon a damping...
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    How to design a PLL locked at 60 Hz

    Hi Friends As an intern, I am designing a PLL which has to lock on to a grid reference signal coming at 60 Hz and has to feed some fets on a solar inverter . The design has a multiplier, a LPF and a VCO. I have searched hundreds of papers but I have not seen any frequencies like this. The...
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    Does anyone has any tutorial fro designing PLL using icap/4

    Hello Everyone I am designing an Analog PLL using icap/4. As I am new to the tool so if someone has a tutorial using the tool or designing a PLL with that tool, please provide me that. Thank you
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    What is the meaning of PLL Lock Range

    Thanks Everyone....Can you please provide me some numerical figures to get a better understanding. With 47 Hz - 63 Hz as the locking range, can you site a VCO center freq and then in that CF and this lock range context, what would be the max. and min. frequencies that the PLL would be able to lock
  13. G

    What is the meaning of PLL Lock Range

    Re: PLL Thanks for your reply So does it means my reference freq. has to fall somewhere between this range and will be in Hz. This PLL is a part of a bigger microprocessor so would not it be too slow if this would be the explanation. Lets say my Fref is 55 Hz so what would be the PLL lock...
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    What is the meaning of PLL Lock Range

    PLL Hi What does it really mean when someone says that the PLL lock range is 47 Hz - 63 Hz? I was thinking that this should be related to the reference freq. which is usually in KHz-MHz range. But as this is in Hz so I am very confused. Does it mean that the reference freq. will be between 47...
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    RF RECEIVER FRONT END LNA DESIGN

    Thank you very much....I read that difference somewhere but still had a doubt..well its confirmed now..thanx
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