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Phase error minimization

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Gagan_SJSU

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Hi All

I have designed a PLL at 60Hz to lock onto AC mains for a solar inverter. I am using a first order filter and I am not able to achieve the phase margin. I have used a higher order filter but things do not work. What else can I do to improve my phase. I can only afford 2degree phase error between my input and output. Please reply.

Thank you
Sunny
 

did you try to add in a zero in the loop filter to improve your phase margin?
 

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