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In OCV(On-Chip Variation) mode, setup check uses the timing delay values from the Max library group for the data and the launch clock network delay. And uses the delay values from the Min library group for the capturing clock network delay assuming that the clocks are set in propagated mode.
HM is not necessary inside the core area.
If only 3, just Drag and Place them into the core.
Pay attention to the HM pins' access metal layer and which side the pins on.
If there are only 32 violations. Just interactive ECO. Adding delay cell (buffer) on the branch that has hold violation.
If too much, let the tools to do 'IPO -hold'.
Re: soc encounter geometry check -short errors in VDD VSS
Check whether the Io Filler's PG pin had been connected to the PG NET.
If not, there need GNC(Global Net Connection).
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