Die to die variation effect on Critical Paths

[dhaval4987]

Dear All,

I want to analyze the effect of die to die process variation effects on critical paths in diigital circuits... Any idea what direction should I start? How to proceed?

even if anyone has not done this but want to participate in discussion, thn most welcome!!!

 

[jpvSoccer]

Hmmm, I would guess that there are a number of process variables that can change between foundry batches; some good and some bad.

How about exporting a critical path as a spice netlist and running montecarlo analysis.

 

[dhaval4987]

Hmmm, I would guess that there are a number of process variables that can change between foundry batches; some good and some bad.

How about exporting a critical path as a spice netlist and running montecarlo analysis.

Hmm... Eventually i was planning to do that. how do I find critical paths in complex digital circuits?

 

[jpvSoccer]

Hi, not sure I understand. STA?

 

[lostinxlation]

I'm not sure from your post if you want to analyze it on the silicon or simulation. if it's on the silicon, you wouldn't want to do it on the random critical paths since it is extremely difficult to evaluate the timing of a specific path on the silicon unless it is designed accordingly. If I were you, I'd create a dummy path that is designed in a way that the timing can be easily evaluated and put a couple of them at the different locations on the chip.
Or maybe you can use a ring oscillator.

 

[flycar]

For STA, there's On-Chip Variation (OCV) Timing Analysis Mode

 

[dhaval4987]

Okay.. now for STA- which one is more convenient to use? Prime Time/Nano Time by Synopsys... or Encounter Timing System by Cadence?

---------- Post added at 09:54 ---------- Previous post was at 09:26 ----------

Yes, STA is not my final aim. But I need to find out the critical path so that I can move ahead. How do you suggest to find out the critical path? Also I would like to see the delay distribution in the circuit....I am not sure if its needed or not- just am curious about.

---------- Post added at 09:54 ---------- Previous post was at 09:54 ----------

Flycar, have you done it? which tool did you use?

 

[lostinxlation]

How do you suggest to find out the critical path?

If you are trying to do it on STA tool, it's easy, but doing it on the silicon is extremely difficult and the critical paths from silicon and STA are often different. LIke i said, you need to create a logic that facilitates the timing analysis and need to put it in the silicon, otherwise, it's nearly impossible to do what you are aiming at.

Also I would like to see the delay distribution in the circuit....I am not sure if its needed or not- just am curious about.

again, it's very easy to do it on STA. But if you are to do it on silicon, I'd probably say not realistic, considering the fact that the timing from so many paths need to be collected.

 

[dhaval4987]

If you are trying to do it on STA tool, it's easy, but doing it on the silicon is extremely difficult and the critical paths from silicon and STA are often different. LIke i said, you need to create a logic that facilitates the timing analysis and need to put it in the silicon, otherwise, it's nearly impossible to do what you are aiming at.

Thanks... does it mean- I have to design a customized path and will test it in STA? Coz what I am going to do- only simulations and test- I am not going to fabricate it and test.

again, it's very easy to do it on STA. But if you are to do it on silicon, I'd probably say not realistic, considering the fact that the timing from so many paths need to be collected.

Which STA tool you would recommed?

 

[lostinxlation]

Thanks... does it mean- I have to design a customized path and will test it in STA? Coz what I am going to do- only simulations and test- I am not going to fabricate it and test.

if you are going to do it on STA, you don't have to make customized paths. Just run STA tool and report the timing and you can find all the violations/slacks in the reports.

Which STA tool you would recommed?

I don't think it matters. Just pick one from major vendors and get used to it.

 

[dhaval4987]

if you are going to do it on STA, you don't have to make customized paths. Just run STA tool and report the timing and you can find all the violations/slacks in the reports.



I don't think it matters. Just pick one from major vendors and get used to it.

Thanks... I will keep asking questions... coz discussing with you makes me clearly see my next step. thanks again.

 

[dhaval4987]

@lostinxlation,

I read the manuals of the timing analysis tools. but now to be frank- I still dont understand how to kick start, do you have any tutorials... or have you done any of these? I dont understand many things like0 where do I get the timing libraries from? how do i provide constraint for the design? etc..

How do I move ahead?

Getting an access for the tool would also be difficult. I am a student right now and I have to check the resources that my university provides...

 

[lostinxlation]

You need to run it by yourself. That's the best way to learn the stuff.
The timing libraries come from whoever makes the standard cells and macros. if you use the cells from ARM, ARM provides it, if you use Virage, they provide it, You might have your own cells in your group and your group might have developped timing library.
Constraint must be made by someone who knows the design, namely you. It's mostly a manual work and may take some time, but it's a necessary step..

 

[dhaval4987]

Okay! So I have made some progress and want another push to move further. I completed STA for a bunch of circuits and have some paths. I did skew analysis and checked that changing a single parameter in model file obviously changes the value of delay but also changes the distribution of critical paths. But now I want a more detailed effects of process variations.

I did STA- exported the critical path of interest as a spice netlist. I plan to run the monte carlo and plan to use HSPICE by synopsys for the same. Is it correct way to handle? If i vary any particular parameter and observe delay variation- will it serve the purpose? Also how do i observe the variation in distribution of critical paths?

 

[dhaval4987]

Also I want to know how to perform within chip (local) and chip to chip (global) variation analysis...

 

[michealwolf]

What's your purpose of doing this? If you want to correlate the STA result with the process variables, I think the key factor would be in the RC extraction. Statical RC extraction is needed.

 

[dhaval4987]

I dont understand. What I want to do is- I want to observe how distribution of critical paths varies and how delay is affected along with process variations. I was advised in the beginning of this thread that I should do STA first and then Monte Carlo.

 

[ebuddy]

Let's simplify the issue first. You are interested in finding out the effect of process variation on delay of digital circuits. There is nothing to do with critical path, because the process variation has the same effect on critical path and non-critical path.

Since the issue is not related to critical path, there is not much value using STA. Any test circuit, say, 2 inverters connecting back-to-back, is typical enough for your analysis. Or you can construct any structure of logic you choose.

The remaining of the your analysis is simple. Run the corner simulation to find out the delay numbers at different process corners.

 

[dhaval4987]

no I have to check the distribution of critical paths. For example- if say top most delay path are labeled as A, B, C and D in one nominal condition, by variations- there will be change in delay ofcourse, but the distribution might change to X, D, B, A.

Also I have a specific path which I found out by STA. Now what should I do to check how delay in that particular path is affected. Just Monte Carlo is what I am planning to do. Does it solve the purpose? Also- how do I check effects of Global and Local variations? Global- among 2 different chips while local is within chip.