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Hi everybody
I am learning to design a vco right now.
In ADS, "harmonic balance" simulation is used to analyze the negative resistance in the circuit. (in ADS2009/example/RFIC/MOS_VCO_prj/NegativeR_test.dsn).
I'd like to do the same thing in cadence. but I got some problems with setup.
at...
for a current source, the output resistance is the larger the better, and this is still useful to the current mirror. It means that, when the output resistance of your current is large, the voltage at the output node will affect the output current little.
Now, let's back to the second chapter...
psrr analysis of single stage amplifier
Hi, everybody
I am reading a paper named as power supply rejection ratio in operational trans-conductance amplifier, and I have question in understanding the equivalent network in it. I hope somebody could explain for me, thanks a lot.
At the first, it...
resently, i recieved some letters to ask me how to determin the numbers of generated samples. Actualy, i determined the numbers by setting the simulation steps. for example, if i set the transient analysis time as 1ms, and simulation step as 1us, the 1ms/1us = 1000 samples will be generated...
usually we calculate the KT/C noise and some other noise of Opamp manually, then add it to the SQNR to get the SNR.
Yes, you can add some verilog-a noise source at the input, but the value of this noise is still calculated manually. So it may not similar to the real chip test. Besides this...
There are several things you need to take into considerations.
1) you need to design a very low bias current reference, usually around 100nA or below.
2)if there is no off-chip capacitor, it's a challenge to make the loop stable. you can search some papers with key words "capacitor-free"...
If you use Cadence Spetre to do the noise analysis, choose the "frequence" as the "sweep variable". After the simulation, you can choose the “Results”->“Print"->"Noise Summary”.Then a "Noise Summary" window will appear. after filling the form, it will show all the noise in the schematic, the...
delsig toolbox
In my mind, "synthesizeNTF" function is in the "delsig" toolbox, not in the "SDtoolbox". To understand the "delsig" toolbox, you can read book "Understanding of Delta-Sigma Data Convertor". There are several matlab codes in chapter 8 which worked perfectly. I think this codes...
Hi, everybody. I have found a method to generate the white noise in Verilog-A. If I let the power density of that white noise equals to KT/C, It may be somehow to represent the KT/C noise, is that alright?
When given 1p F capacitor, the mean square root of noise with such code is 6.079e-5V...
Hi, everybody.
I am simulating a delta-sigma ADC with Verilog-A model. I try to add the kT/C noise into the transient analysis. Does anybody know how to set up a kT/C noise verilogA model, which support the transient analysis.
Thanks very much.
how synthesizentf works
There is a book named "Understanding Delta-Sigma Data Convertors" tells you how the toolbox calculates the optimized poles. The material is in the chapter 8.1.1 "how synthesizeNTF works". The author, Richard Schreier of this book wrote the "delsig" toolbox.
Hi, everybody. I am using matlab toolbox "delsig" to do the system design of a second order ADC.
In the "delsig" toolbox, function " realizeNTF ( ntf, form, stf ) " can set the coefficients for a particular modulator topology. It works perfectly with default input "stf=1", but when I set the...
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