low quiescent current LDO design?

[xinhunlei]

Hi ,everyone ,i will design an on chip LDO ,the spec is vout=3.3v vin=4.4v-5.5v,i think these spec is easy to achieve ,
but it require IQ only 2uA,i have difficulty ! one who have some ideas or give me some papers to refrence? thanks a lot!

 

[renwl]

how much are the output current?

 

[xinhunlei]

output current is only 5mA

 

[iamxo]

I think you just need to design a low supply current EA to satisfy the specification.

maybe the EA should be in subthreshold region.

 

[IamnotJunk]

what does the IC paperwork says?

 

[fatcat1205]

There are several things you need to take into considerations.
1) you need to design a very low bias current reference, usually around 100nA or below.

2)if there is no off-chip capacitor, it's a challenge to make the loop stable. you can search some papers with key words "capacitor-free".

3)Since the output current is only 5mA, the power transistor will not be too large, but the error-amplifier should have enough output current to charge or discharge the gate-capacitor of the power transistor. The Slew-Rate of the error-amplifier is very important.

4)there are some paper about the slew-rate enhancement circuit, which can help the error-amplifier to charge the power transistor with less quiescent current. you can search the paper with key words "SRE" or "Slew-Rate enhancement".

 

[xinhunlei]

I do not understand how to consider to use a low supply current EA to my design,can you tell me some details?
To IamnotJunk:What do you mean,please?
The most thing i worry is the stablity under such low IQ. Furthermore,if I use a bandgap to realize the reference ,is this possible?What kind ofrefrence can I use in this low IQ LDO design while it's PSRR is large?

 

[sudheer_vlsi]

Lekage itself will be comparable to ur quiscent current. i donno how one can design with 2uA of Current.

 

[arghpok]

It is possible to design a 2uA Iq LDO, but it hasn't been done yet. I know this because I'm working on it. For ur reference, u need to use subVth reference like Giuseppe de Vita & Giuseppe Iannaconne vref, which are nanopower 10 ppm vrefs, or curvature corrected subvth vref. but this last ones take too much area (large resistors). Typical error amplifier biasing are no longer suitable for this kind of applications, and u must operate in subvth all the time. Since this will deteriorate the speed of the circuit (although ur LDO wont source too much current), u need dynamically active current sink/source for the parasitic capacitance of Mpass. this can be achieved with gm cells in common gate config. I'm achieving 1.6 uA of Iq at all range of Iout (0-100mA). But, there is a big problem not yet fixed: PSRR. PSRR at mid band freq aproaches 0dB, and that's well, just very very bad

That's all I can say about this kind of circuits.

 

[jt_rf]

I have seen few BGR implementation with current of 1.4uA. I think still it will be a challenge to implement.

"Very Low Power High Temperature Stability Bandgap Reference Voltage" by W. Rahajandraibe, D. Auvergne, C. Dufaza & B. Cialdella, B. Majoux and V. Chowdhury

just search this paper and would be useful for BGR design of LDO.

 

[arghpok]

Yeah, right, but we're talking about regulators, not references, the references (i.e. bandgap) don't need to provide any current to a load, because they help to bias, not to source.

 

[jt_rf]

I felt BGR current is also part of LDO Iq apart from Err amp. Thats how we do designs here..