fatcat1205
Newbie level 6
psrr analysis of single stage amplifier
Hi, everybody
I am reading a paper named as power supply rejection ratio in operational trans-conductance amplifier, and I have question in understanding the equivalent network in it. I hope somebody could explain for me, thanks a lot.
At the first, it gives an schematic for two stage OTA, in such schematic, the second stage is a single stage common-source amplifier. But in the following figure, the second stage turns out to be a differential input single output amplifier. I try to understand the circuit in this way: the gate of the input transistor, M5, is the inverting input for the operational amplifer, and source of M5 is the non-inverting input, but there is still a path from VDD to the amplifier in the equivalent network, and my understanding fails to explain this one. And in the paper, the gain from VDD to Vout of the second stage is defined when both inverting and non-inverting inputs are ac-grounded, so if either of this two input port is the source of M5, there will be no path from VDD to Vout.
I hope somebody will explain the non-inverting input in the equivalent network for me. Thanks again.
Hi, everybody
I am reading a paper named as power supply rejection ratio in operational trans-conductance amplifier, and I have question in understanding the equivalent network in it. I hope somebody could explain for me, thanks a lot.
At the first, it gives an schematic for two stage OTA, in such schematic, the second stage is a single stage common-source amplifier. But in the following figure, the second stage turns out to be a differential input single output amplifier. I try to understand the circuit in this way: the gate of the input transistor, M5, is the inverting input for the operational amplifer, and source of M5 is the non-inverting input, but there is still a path from VDD to the amplifier in the equivalent network, and my understanding fails to explain this one. And in the paper, the gain from VDD to Vout of the second stage is defined when both inverting and non-inverting inputs are ac-grounded, so if either of this two input port is the source of M5, there will be no path from VDD to Vout.
I hope somebody will explain the non-inverting input in the equivalent network for me. Thanks again.
