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Recent content by fail1

  1. F

    ICG cells placement in the design

    Should we place ICG cells close to the clock root or should we place next to the flop to avoid skew? Thx Kumar
  2. F

    Scan shift and capture timing

    How can we verify scan shift and capture timing in a design? --Kumar
  3. F

    ISO cells in always on logic?

    Thanks for the reply!
  4. F

    ISO cells in always on logic?

    When doing Low Power, why the Isolation cell need to be placed in always-on logic? Thx Kumar
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    what are Multicut vias & advantage of it?

    What is the advantage of multicut vias over single cut vias? Thanks Kumar
  6. F

    Common ques asked regarding CTS in the interviews?

    How do u balance the clocks during CTS? How do u start answering this question & what all topics we should cover while answering this question? Thanks Kumar
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    Logical Pin Name used

    Its Conformal. Its just a warning.No problem in processing the testcase. I jsut want to understand what exactly this warning message means? Thx Meena
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    Logical Pin Name used

    Hello, I am getting this message: Logical Pin Name used :u_xx/clk1 Verification Tool complains that create_clock in your sdc file is using a logical pin name. create_clock [get_pins u_xx/clk1] -name clk1 -period 25 What does it mean ? Thanks Kumar
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    Timing constriants difference between functional and test m

    Re: Timing constriants difference between functional and te Those are good points. I read that sometimes center aligned clocking in functional mode become edge aligned clocking in test mode also complicates the timing closure between test & functional mode. I couldnt understand the reason...
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    What is meant by Clock Uncertainty?

    Before CTS, the clocks are not real or basically, the clock is in ideal state. We assume that the clock reaches to all the flops at the same time i.e. no skew . To model the effect of skew, we use uncertainity values. So, we build these uncertainity margins for setup & hold & check our timing...
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    Correlation between signoff & implementation flow

    Hi, Say, I have done Place & route for my design using Cadence/Magma & doing signoff checks now. What are all the things to look for if you see a correlation issue between implementation & signoff tools? Is there any doc/white paper which explains all the key points to debug the issue? Thx Kumar
  12. F

    Virtuoso : metal layers being used

    Is there any skill program to get the info about all the metal layers being used? Or do I have to to CntrlF & then look into the GUI & get the layers being present in that cell in Virtuoso?
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    Virtuoso : metal layers being used

    Hello, Say, I have imported my GDS in virtuoso & I am looking at the layout view. Is there a way to dump out all the metal layers being used? Thx Kumar
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    difference between spefs with & without noise?

    What is the difference between the spef generated before noise analysis & one generated after noise optimisation? eg After postroute optimisation, if you generate a spef & then you generate another spef after doing SI optimisation.What is the diff in these 2 spefs?
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    interview question regarding clock skew

    Hi, I am assuming that the repowering cells which you mentioned are the clock buffers cell used by CTS.But if the clock network is fixed, how can that route be detoured after routing...isnt that net across the macro will be a fixed net if its a clock net. Thanks Kumar
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