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Great question. If I understand you correctly, the reason is related to my item #1 above. In test mode, the clock sources may be (often are) very different from those in functional mode.fail1 said:Those are good points.
I read that sometimes center aligned clocking in functional mode become edge aligned clocking in test mode also complicates the timing closure between test & functional mode.
I couldnt understand the reason behind this.Why can the clock phase be different between test & functional mode?
Thx
Meena
For example: in functional mode, data is exchanged between clock domain A and clock domain B. But in test mode, they are separate scan chains, so all paths form A <-> B are false paths. Maybe not a great example since you would want to try to test those paths in test mode too, but it's not always possible to do so.engr said:Thanks randyest
could you pls elobrate/give scenario where false and multi cycle paths are different in test mode comapred to funcational mode