Logical Pin Name used

[fail1]

Hello,

I am getting this message:
Logical Pin Name used :u_xx/clk1

Verification Tool complains that create_clock in your sdc file is using a logical pin name.

create_clock [get_pins u_xx/clk1] -name clk1 -period 25

What does it mean ?

Thanks
Kumar

 

[randyest]

Which verification tool? What is the exact message? Is it a warning or an error? Does it prevent further processing? Does the tool prefer 'get_ports' SDC command instead of 'get_pins'?

 

[fail1]

Its Conformal.
Its just a warning.No problem in processing the testcase.
I jsut want to understand what exactly this warning message means?

Thx
Meena

 

[randyest]

I think it means your constraint file creates a clock on a logical pin rather than a physical pin. i.e., some hierarchy module / pin name, which could be removed from the design by flattening or physical design.

I think it's best practice for SDC to work with cell/pin_name instead of module/pin_name, and Conformal is trying to tell you this.

 

[ljxpjpjljx]

right, you can try to use pin name instead!

 

[shitansh]

Its Conformal.
Its just a warning.No problem in processing the testcase.
I jsut want to understand what exactly this warning message means?

Thx
Meena

create_clock [get_pins u_xx/clk1] -name clk1 -period 25

In this constraint get_pins is object access command which should be physical port/pin of your module and -name should be name of net connected with physical pin.

If any of these mismatches you will get this kind of waring.

HTH
Shitansh Vaghela